GICD_CPENDSGIR<n>, SGI Clear-Pending Registers, n = 0 - 3
The GICD_CPENDSGIR<n> characteristics are:
Purpose
Removes the pending state from an SGI.
A write to this register changes the state of a pending SGI to inactive, and the state of an active and pending SGI to active.
Configuration
Four SGI clear-pending registers are implemented. Each register contains eight clear-pending bits for each of four SGIs, for a total of 16 possible SGIs.
In multiprocessor implementations, each PE has a copy of these registers.
Attributes
GICD_CPENDSGIR<n> is a 32-bit register.
Field descriptions
The GICD_CPENDSGIR<n> bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SGI_clear_pending_bits3 | SGI_clear_pending_bits2 | SGI_clear_pending_bits1 | SGI_clear_pending_bits0 | ||||||||||||||||||||||||||||
SGI_clear_pending_bits<x>, bits [8x+7:8x], for x = 3 to 0
Removes the pending state from SGI number 4n + x for the PE corresponding to the bit number written to.
Reads and writes have the following behavior:
| SGI_clear_pending_bits<x> | Meaning |
|---|---|
| 0x00 | If read, indicates that the SGI from the corresponding PE is not pending and is not active and pending. If written, has no effect. |
| 0x01 | If read, indicates that the SGI from the corresponding PE is pending or is active and pending. If written, removes the pending state from the SGI for the corresponding PE. |
On a Warm reset, this field resets to 0.
For SGI ID m, generated by processing element C writing to the corresponding GICD_SGIR field, where DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_CPENDSGIR<n> number is given by n = m DIV 4.
- The offset of the required register is (0xF10 + (4n)).
- The offset of the required field within the register GICD_CPENDSGIR<n> is given by m MOD 4.
- The required bit in the 8-bit SGI clear-pending field m is bit C.
Accessing the GICD_CPENDSGIR<n>
These registers are used only when affinity routing is not enabled. When affinity routing is enabled, this register is RES0. An implementation is permitted to make the register RAZ/WI in this case.
A register bit that corresponds to an unimplemented SGI is RAZ/WI.
These registers are byte-accessible.
If the GIC implementation supports two Security states:
- A register bit that corresponds to a Group 0 interrupt is RAZ/WI to Non-secure accesses.
- Register bits corresponding to unimplemented PEs are RAZ/WI.
GICD_CPENDSGIR<n> can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Distributor | 0x0F10 + (4 * n) | GICD_CPENDSGIR<n> |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.