GICR_ICACTIVER0, Interrupt Clear-Active Register 0
The GICR_ICACTIVER0 characteristics are:
Deactivates the corresponding SGI or PPI. These registers are used when saving and restoring GIC state.
A copy of this register is provided for each Redistributor.
GICR_ICACTIVER0 is a 32-bit register.
The GICR_ICACTIVER0 bit assignments are:
Clear_active_bit<x>, bit [x], for x = 31 to 0
Removes the active state from interrupt number x. Reads and writes have the following behavior:
If read, indicates that the corresponding interrupt is not active, and is not active and pending.
If written, has no effect.
If read, indicates that the corresponding interrupt is active, or is active and pending.
If written, deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the GICR_ICACTIVER0
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICACTIVER0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ICACTIVER<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ICACTIVER<n>.
When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.
GICR_ICACTIVER0 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.