GICR_ICENABLER0, Interrupt Clear-Enable Register 0
The GICR_ICENABLER0 characteristics are:
Disables forwarding of the corresponding SGI or PPI to the CPU interfaces.
A copy of this register is provided for each Redistributor.
GICR_ICENABLER0 is a 32-bit register.
The GICR_ICENABLER0 bit assignments are:
Clear_enable_bit<x>, bit [x], for x = 31 to 0
For PPIs and SGIs, controls the forwarding of interrupt number x to the CPU interfaces. Reads and writes have the following behavior:
If read, indicates that forwarding of the corresponding interrupt is disabled.
If written, has no effect.
If read, indicates that forwarding of the corresponding interrupt is enabled.
If written, disables forwarding of the corresponding interrupt.
After a write of 1 to this bit, a subsequent read of this bit returns 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the GICR_ICENABLER0
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICENABLER0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ICENABLER<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ICENABLER<n>.
When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.
GICR_ICENABLER0 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.