GICR_ICFGR1, Interrupt Configuration Register 1
The GICR_ICFGR1 characteristics are:
Determines whether the corresponding PPI is edge-triggered or level-sensitive.
A copy of this register is provided for each Redistributor.
For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE.
Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state.
GICR_ICFGR1 is a 32-bit register.
The GICR_ICFGR1 bit assignments are:
Int_config<x>, bits [2x+1:2x], for x = 15 to 0
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config (bit [2x]) is RES0.
Possible values of Int_config (bit [2x+1]) are:
Corresponding interrupt is level-sensitive.
Corresponding interrupt is edge-triggered.
A read of this bit always returns the correct value to indicate the interrupt triggering method.
For PPIs, Int_config is programmable unless the implementation supports two Security states and the bit corresponds to a Group 0 or Secure Group 1 interrupt, in which case the bit is RAZ/WI to Non-secure accesses.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the GICR_ICFGR1
This register is used when affinity routing is enabled.
When affinity routing is disabled for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICD_ICFGR<n> with n=1 .
GICR_ICFGR1 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.