GICR_INVALLR, Redistributor Invalidate All Register
The GICR_INVALLR characteristics are:
Purpose
Invalidates any cached configuration data of all physical LPIs, causing the GIC to reload the interrupt configuration from the physical LPI Configuration table at the address specified by GICR_PROPBASER.
Configuration
A copy of this register is provided for each Redistributor.
Attributes
GICR_INVALLR is a 64-bit register.
Field descriptions
The GICR_INVALLR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| V | RES0 | vPEID | |||||||||||||||||||||||||||||
| RES0 | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
V, bit [63]
When FEAT_GICv4p1 is implemented:
When FEAT_GICv4p1 is implemented:
Indicates whether the INTID is virtual or physical.
| V | Meaning |
|---|---|
| 0b0 |
Invalidate is for a physical INTID. |
| 0b1 |
Invalidate is for a virtual INTID. |
Otherwise:
Otherwise:
Reserved, RES0.
Bits [62:48]
Reserved, RES0.
vPEID, bits [47:32]
When FEAT_GICv4p1 is implemented:
When FEAT_GICv4p1 is implemented:
When GICR_INVLPIR.V == 0, this field is RES0
When GICR_INVLPIR.V == 1, this field is the target vPEID of the invalidate.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields. Unimplemented bits are RES0.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [31:0]
Reserved, RES0.
If any LPI has been forwarded to the PE and a valid write to GICR_INVALLR is received, the Redistributor must ensure it reloads its properties from memory. This has no effect on the forwarded LPI if it has already been activated.
Accessing the GICR_INVALLR
This register is mandatory when any of the following are true:
- GICR_TYPER.Direct is 1.
- GICR_CTLR.IR is 1.
- GICv4.1 is implemented.
Otherwise, the functionality is IMPLEMENTATION DEFINED.
Writes to this register have no effect if no physical LPIs are currently stored in the local Redistributor cache.
GICR_INVALLR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x00B0 | GICR_INVALLR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.