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GICR_INVALLR, Redistributor Invalidate All Register

The GICR_INVALLR characteristics are:

Purpose

Invalidates any cached configuration data of all physical LPIs, causing the GIC to reload the interrupt configuration from the physical LPI Configuration table at the address specified by GICR_PROPBASER.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_INVALLR is a 64-bit register.

Field descriptions

The GICR_INVALLR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
VRES0vPEID
RES0
313029282726252423222120191817161514131211109876543210

V, bit [63]

When FEAT_GICv4p1 is implemented:

Indicates whether the INTID is virtual or physical.

VMeaning
0b0

Invalidate is for a physical INTID.

0b1

Invalidate is for a virtual INTID.


Otherwise:

Reserved, RES0.

Bits [62:48]

Reserved, RES0.

vPEID, bits [47:32]

When FEAT_GICv4p1 is implemented:

When GICR_INVLPIR.V == 0, this field is RES0

When GICR_INVLPIR.V == 1, this field is the target vPEID of the invalidate.

Note

The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields. Unimplemented bits are RES0.


Otherwise:

Reserved, RES0.

Bits [31:0]

Reserved, RES0.

Note

If any LPI has been forwarded to the PE and a valid write to GICR_INVALLR is received, the Redistributor must ensure it reloads its properties from memory. This has no effect on the forwarded LPI if it has already been activated.

Accessing the GICR_INVALLR

This register is mandatory when any of the following are true:

Otherwise, the functionality is IMPLEMENTATION DEFINED.

Writes to this register have no effect if no physical LPIs are currently stored in the local Redistributor cache.

GICR_INVALLR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorRD_base0x00B0GICR_INVALLR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are WO.
  • When an access is Secure accesses to this register are WO.
  • When an access is Non-secure accesses to this register are WO.