PMSWINC_EL0, Performance Monitors Software Increment register
The PMSWINC_EL0 characteristics are:
Purpose
Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see SW_INCR.
Configuration
External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMSWINC_EL0[31:0] .
External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMSWINC[31:0] .
PMSWINC_EL0 is in the Core power domain.
Implementation of this register is OPTIONAL.
If this register is implemented, use of it is deprecated.
If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface.
Attributes
PMSWINC_EL0 is a 32-bit register.
Field descriptions
The PMSWINC_EL0 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Bit [31]
Reserved, RES0.
P<n>, bit [n], for n = 30 to 0
Event counter software increment bit for PMEVCNTR<n>_EL0.
If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are WI.
| P<n> | Meaning |
|---|---|
| 0b0 |
No action. The write to this bit is ignored. |
| 0b1 |
It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter n. |
Accessing the PMSWINC_EL0
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
PMSWINC_EL0 can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| PMU | 0xCA0 | PMSWINC_EL0 |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and SoftwareLockStatus() accesses to this register are WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and !SoftwareLockStatus() accesses to this register are WO.
- Otherwise accesses to this register generate an error response.