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HMAIR1, Hyp Memory Attribute Indirection Register 1

The HMAIR1 characteristics are:

Purpose

Along with HMAIR0, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations for memory accesses from Hyp mode.

AttrIndx[2] indicates the HMAIR register to be used:

  • When AttrIndx[2] is 0, HMAIR0 is used.
  • When AttrIndx[2] is 1, HMAIR1 is used.

Configuration

AArch32 System register HMAIR1 bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL2[63:32] .

This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to HMAIR1 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

HMAIR1 is a 32-bit register.

Field descriptions

The HMAIR1 bit assignments are:

When TTBCR.EAE == 1:
313029282726252423222120191817161514131211109876543210
Attr7Attr6Attr5Attr4

Attr<n>, bits [8(n-4)+7:8(n-4)], for n = 7 to 4

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

  • AttrIndx[2:0] gives the value of <n> in Attr<n>.
  • AttrIndx[2] defines which MAIR to access. Attr7 to Attr4 are in MAIR1, and Attr3 to Attr0 are in MAIR0.

Bits [7:4] are encoded as follows:

Attr<n>[7:4]Meaning
0b0000Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
0b00RW, RW not0b00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RW, RW not0b00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

The meaning of bits [3:0] depends on the value of bits [7:4]:

Attr<n>[3:0]Meaning when Attr<n>[7:4] is0b0000Meaning when Attr<n>[7:4] is not0b0000
0b0000Device-nGnRnE memoryUNPREDICTABLE
0b00RW, RW not0b00UNPREDICTABLENormal memory, Inner Write-Through Transient
0b0100Device-nGnRE memoryNormal memory, Inner Non-cacheable
0b01RW, RW not0b00UNPREDICTABLENormal memory, Inner Write-Back Transient
0b1000Device-nGRE memoryNormal memory, Inner Write-Through Non-transient (RW=0b00)
0b10RW, RW not0b00UNPREDICTABLENormal memory, Inner Write-Through Non-transient
0b1100Device-GRE memoryNormal memory, Inner Write-Back Non-transient (RW=0b00)
0b11RW, RW not0b00UNPREDICTABLENormal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in some Attr<n> fields have the following meanings:

R or WMeaning
0b0No Allocate
0b1Allocate

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the HMAIR1

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b1000b10100b00100b001
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    return HMAIR1;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        return HMAIR1;
              

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b1000b10100b00100b001
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    HMAIR1 = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        HMAIR1 = R[t];