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ID_ISAR6, Instruction Set Attribute Register 6

The ID_ISAR6 characteristics are:

Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4 and ID_ISAR5.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

Configuration

AArch32 System register ID_ISAR6 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR6_EL1[31:0] .

This register is present only from Armv8.2. Otherwise, direct accesses to ID_ISAR6 are RES0 from EL1, EL2, and EL3.

Attributes

ID_ISAR6 is a 32-bit register.

Field descriptions

The ID_ISAR6 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0I8MMBF16SPECRESSBFHMDPJSCVT

Bits [31:28]

Reserved, RES0.

I8MM, bits [27:24]

When ARMv8.2-AA32I8MM is implemented:

Indicates support for Advanced SIMD and floating-point Int8 matrix multiplication instructions in AArch32 state. Defined values are:

I8MMMeaning
0b0000

Int8 matrix multiplication instructions are not implemented.

0b0001

VSMMLA, VSUDOT, VUMMLA, VUSMMLA, and VUSDOT instructions are implemented.

All other values are reserved.

ARMv8.2-AA32I8MM implements the functionality identified by 0b0001.


Otherwise:

Reserved, RES0.

BF16, bits [23:20]

When ARMv8.2-AA32BF16 is implemented:

Indicates support for Advanced SIMD and floating-point BFloat16 instructions in AArch32 state. Defined values are:

BF16Meaning
0b0000

BFloat16 instructions are not implemented.

0b0001

VCVT, VCVTB, VCVTT, VDOT, VFMAL, and VMMLA instructions with BF16 operand or result types are implemented.

All other values are reserved.

ARMv8.2-AA32BF16 implements the functionality identified by 0b0001.


Otherwise:

Reserved, RES0.

SPECRES, bits [19:16]

Indicates support for Speculation invalidation instructions in AArch32 state. Defined values are:

SPECRESMeaning
0b0000

CFPRCTX, DVPRCTX, and CPPRCTX instructions are not implemented.

0b0001

CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

SB, bits [15:12]

Indicates support for SB instruction in AArch32 state. Defined values are:

SBMeaning
0b0000

SB instruction is not implemented.

0b0001

SB instruction is implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

FHM, bits [11:8]

From Armv8.2:

Indicates support for Advanced SIMD and floating-point VFMAL and VFMSL instructions in AArch32 state. Defined values are:

FHMMeaning
0b0000

VFMAL and VMFSL instructions not implemented.

0b0001

VFMAL and VMFSL instructions implemented.

ARMv8.2-FHM implements the functionality identified by the value 0b0001.


Otherwise:

Reserved, RES0.

DP, bits [7:4]

From Armv8.2:

Indicates support for dot product instructions in AArch32 state. Defined values are:

DPMeaning
0b0000

No dot product instructions implemented.

0b0001

VUDOT and VSDOT instructions implemented.

All other values are reserved.

ARMv8.2-DotProd implements the functionality identified by the value 0b0001.


Otherwise:

Reserved, RES0.

JSCVT, bits [3:0]

From Armv8.3:

Indicates support for the Javascript conversion instruction in AArch32 state. Defined values are:

JSCVTMeaning
0b0000

The VJCVT instruction is not implemented.

0b0001

The VJCVT instruction is implemented.

All other values are reserved.

In Armv8.0, Armv8.1 and Armv8.2 the only permitted value is 0b0000.

From Armv8.3 the only permitted value is 0b0001. This feature is identified as ARMv8.3.JSConv.


Otherwise:

Reserved, RES0.

Accessing the ID_ISAR6

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b00000b00100b111
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() && ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6 trapped by HCR.TID3") && HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        return ID_ISAR6;
elsif PSTATE.EL == EL2 then
    return ID_ISAR6;
elsif PSTATE.EL == EL3 then
    return ID_ISAR6;
              


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