ID_PFR1, Processor Feature Register 1
The ID_PFR1 characteristics are:
Purpose
Gives information about the AArch32 programmers' model.
Must be interpreted with ID_PFR0.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.
Configuration
AArch32 System register ID_PFR1 bits [31:0] are architecturally mapped to AArch64 System register ID_PFR1_EL1[31:0] .
Attributes
ID_PFR1 is a 32-bit register.
Field descriptions
The ID_PFR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GIC | Virt_frac | Sec_frac | GenTimer | Virtualization | MProgMod | Security | ProgMod |
GIC, bits [31:28]
System register GIC CPU interface. Defined values are:
GIC | Meaning |
---|---|
0b0000 |
GIC CPU interface system registers not implemented. |
0b0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
0b0011 |
System register interface to version 4.1 of the GIC CPU interface is supported. |
All other values are reserved.
Virt_frac, bits [27:24]
Virtualization fractional field. When the Virtualization field is 0b0000, determines the support for features from the ARMv7 Virtualization Extensions. Defined values are:
Virt_frac | Meaning |
---|---|
0b0000 |
No features from the ARMv7 Virtualization Extensions are implemented. |
0b0001 |
The following features of the ARMv7 Virtualization Extensions are implemented: |
All other values are reserved.
In Armv8-A the permitted values are:
- 0b0000 when EL2 is implemented.
- 0b0001 when EL2 is not implemented.
This field is only valid when the value of ID_PFR1.Virtualization is 0, otherwise it holds the value 0b0000.
The ID_ISAR registers do not identify whether the instructions added by the ARMv7 Virtualization Extensions are implemented.
Sec_frac, bits [23:20]
Security fractional field. When the Security field is 0b0000, determines the support for features from the ARMv7 Security Extensions. Defined values are:
Sec_frac | Meaning |
---|---|
0b0000 |
No features from the ARMv7 Security Extensions are implemented. |
0b0001 |
The following features from the ARMv7 Security Extensions are implemented: |
0b0010 |
As for 0b0001, plus the ability to access Secure or Non-secure physical memory is supported. |
All other values are reserved.
In Armv8-A the permitted values are:
- 0b0000 when EL3 is implemented.
- 0b0001 or 0b0010 when EL3 is not implemented.
This field is only valid when the value of ID_PFR1.Security is 0, otherwise it holds the value 0b0000.
GenTimer, bits [19:16]
Generic Timer support. Defined values are:
GenTimer | Meaning |
---|---|
0b0000 |
Generic Timer is not implemented. |
0b0001 |
Generic Timer is implemented. |
0b0010 |
Generic Timer is implemented, and also includes support for CNTHCTL.EVNTIS and CNTKCTL.EVNTIS fields, and CNTPCTSS and CNTVCVSS counter views. |
All other values are reserved.
ARMv8.6-ECV implements the functionality identified by the value 0b0010.
From Armv8.0 to Armv8.4, the only permitted value is 0b0001.
From Armv8.6, the only permitted value is 0b0010.
Virtualization, bits [15:12]
Virtualization support. Defined values are:
Virtualization | Meaning |
---|---|
0b0000 |
EL2, Hyp mode, and the HVC instruction not implemented. |
0b0001 |
EL2, Hyp mode, the HVC instruction, and all the features described by Virt_frac == 0b0001 implemented. |
All other values are reserved.
In Armv8-A the permitted values are:
- 0b0000 when EL2 is not implemented.
- 0b0001 when EL2 is implemented.
In an implementation that includes EL2, if EL2 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0b0001.
The ID_ISARs do not identify whether the HVC instruction is implemented.
MProgMod, bits [11:8]
M profile programmers' model support. Defined values are:
MProgMod | Meaning |
---|---|
0b0000 |
Not supported. |
0b0010 |
Support for two-stack programmers' model. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0000.
Security, bits [7:4]
Security support. Defined values are:
Security | Meaning |
---|---|
0b0000 |
EL3, Monitor mode, and the SMC instruction not implemented. |
0b0001 |
EL3, Monitor mode, the SMC instruction, and all the features described by Sec_frac == 0b0001 implemented. |
0b0010 |
As for 0b0001, and adds the ability to set the NSACR.RFR bit. Not permitted in Armv8 as the NSACR.RFR bit is RES0. |
All other values are reserved.
In Armv8-A the permitted values are:
- 0b0000 when EL3 is not implemented.
- 0b0001 when EL3 is implemented.
In an implementation that includes EL3, if EL3 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0b0001.
ProgMod, bits [3:0]
Support for the standard programmers' model for ARMv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes. Defined values are:
ProgMod | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Supported. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Accessing the ID_PFR1
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_PFR1; elsif PSTATE.EL == EL2 then return ID_PFR1; elsif PSTATE.EL == EL3 then return ID_PFR1;