PRRR, Primary Region Remap Register
The PRRR characteristics are:
Purpose
Controls the top level mapping of the TEX[0], C, and B memory region attributes.
Configuration
AArch32 System register PRRR bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[31:0] when TTBCR.EAE == 0.
MAIR0 and PRRR are the same register, with a different view depending on the value of TTBCR.EAE:
- When it is set to 0, the register is as described in PRRR.
- When it is set to 1, the register is as described in MAIR0.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
PRRR is a 32-bit register.
Field descriptions
The PRRR bit assignments are:
When TTBCR.EAE == 0:
NOS<n>, bit [n+24], for n = 0 to 7
Not Outer Shareable. NOS<n> is the Outer Shareable property for memory attributes n, if the region is mapped as Normal memory that is not Inner Non-cacheable, Outer Non-cacheable, and the appropriate PRRR.{NS0, NS1} field identifies the region as shareable. n is the value of the concatenation of the {TEX[0], C, B} bits from the translation table descriptor. The possible values of each NOS<n> field other than NOS6 are:
NOS<n> | Meaning |
---|---|
0b0 |
Memory region is Outer Shareable. |
0b1 |
Memory region is Inner Shareable. |
The value of this bit is ignored if the region is:
- Device memory
- Normal memory that is at least one of:
- Inner Non-cacheable, Outer Non-cacheable.
- Identified by the appropriate PRRR.{NS0, NS1} field as Non-shareable.
The meaning of the NOS6 field is IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
Bits [23:20]
Reserved, RES0.
NS1, bit [19]
Mapping of S = 1 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:
- Is not Inner Non-cacheable, Outer Non-cacheable.
- Has the S bit in the translation table descriptor set to 1.
The possible values of this bit are:
NS1 | Meaning |
---|---|
0b0 |
Region is Non-shareable. |
0b1 |
Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. |
This field resets to an architecturally UNKNOWN value.
NS0, bit [18]
Mapping of S = 0 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:
- Is not Inner Non-cacheable, Outer Non-cacheable.
- Has the S bit in the translation table descriptor set to 0.
The possible values of this bit are:
NS0 | Meaning |
---|---|
0b0 |
Region is Non-shareable. |
0b1 |
Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. |
This field resets to an architecturally UNKNOWN value.
DS1, bit [17]
Mapping of S = 1 attribute for Device memory. From Armv8, all types of Device memory are Outer Shareable, and therefore this bit is RES1.
This field resets to an architecturally UNKNOWN value.
DS0, bit [16]
Mapping of S = 0 attribute for Device memory. From Armv8, all types of Device memory are Outer Shareable, and therefore this bit is RES1.
This field resets to an architecturally UNKNOWN value.
TR<n>, bits [2n+1:2n], for n = 0 to 7
TR<n> is the primary TEX mapping for memory attributes n, and defines the mapped memory type for a region with attributes n. n is the value of the concatenation of the {TEX[0], C, B} bits from the translation table descriptor. The possible values for each field other than TR6 are:
TR<n> | Meaning |
---|---|
0b00 |
Device-nGnRnE memory |
0b01 |
Device-nGnRE memory |
0b10 |
Normal memory |
The value 0b11 is reserved. The effect of programming a field to 0b11 is CONSTRAINED UNPREDICTABLE, see 'Unallocated values in fields of AArch32 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11.
The meaning of the TR6 field is IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
Accessing the PRRR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '0' then return PRRR_S; else return PRRR_NS; else return PRRR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then return PRRR_NS; else return PRRR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then return PRRR_S; else return PRRR_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '0' then PRRR_S = R[t]; else PRRR_NS = R[t]; else PRRR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then PRRR_NS = R[t]; else PRRR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; else if SCR.NS == '0' then PRRR_S = R[t]; else PRRR_NS = R[t];