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CPTR_EL3, Architectural Feature Trap Register (EL3)

The CPTR_EL3 characteristics are:

Purpose

Controls trapping to EL3 of access to CPACR_EL1, CPTR_EL2, trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution. Also controls EL3 access to trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution.

Configuration

This register is present only when HaveEL(EL3). Otherwise, direct accesses to CPTR_EL3 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CPTR_EL3 is a 64-bit register.

Field descriptions

The CPTR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
TCPACTAMRES0TTARES0TFPRES0EZRES0
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

TCPAC, bit [31]

Traps all of the following to EL3, from both Security states and both Execution states.

  • EL2 accesses to CPTR_EL2, reported using EC syndrome value 0x18, or HCPTR, reported using EC syndrome value 0x03.
  • EL2 and EL1 accesses to CPACR_EL1 reported using EC syndrome value 0x18, or CPACR reported using EC syndrome value 0x03.

When CPTR_EL3.TCPAC is:

TCPACMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.

This field resets to an architecturally UNKNOWN value.

TAM, bit [30]

When AMUv1 is implemented:

Trap Activity Monitor access. Traps EL2, EL1 and EL0 accesses to all Activity Monitor registers to EL3.

Accesses to the Activity Monitors registers are trapped as follows:

TAMMeaning
0b0

Accesses from EL2, EL1, and EL0 to Activity Monitor registers are not trapped.

0b1

Accesses from EL2, EL1, and EL0 to Activity Monitor registers are trapped to EL3.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [29:21]

Reserved, RES0.

TTA, bit [20]

Traps System register accesses. Accesses to the trace registers, from all Exception levels, both Security states, and both Execution states are trapped to EL3 as follows:

  • In AArch64 state, Trace registers with op0=2, op1=1, are trapped to EL3 and reported using EC syndrome value 0x18.

  • In AArch32 state, accesses using MCR or MRC to the Trace registers with cpnum=14 and opc1=1 are reported using EC syndrome value 0x05.

  • In AArch32 state, accesses using MCRR or MRRC to the Trace registers with cpnum=14 and opc1=1 are reported using EC syndrome value 0x0C.

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any System register access to the trace registers is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPACR.TRCDIS, CPACR_EL1.TTA or CPTR_EL2.TTA.

If System register access to trace functionality is not supported, this bit is RES0.

Note

The ETMv4 architecture does not permit EL0 to access the trace registers. If the Armv8-A architecture is implemented with an ETMv4 implementation, EL0 accesses to the trace registers are UNDEFINED, and any resulting exception is higher priority than this trap exception.

EL3 does not provide traps on trace register accesses through the Memory-mapped interface.

System register accesses to the trace registers can have side-effects. When a System register access is trapped, no side-effects occur before the exception is taken, see 'Register access instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

This field resets to an architecturally UNKNOWN value.

Bits [19:11]

Reserved, RES0.

TFP, bit [10]

Traps all accesses to SVE, Advanced SIMD and floating-point functionality, from all Exception levels, both Security states, and both Execution states, to EL3. Defined values are:

This includes the following registers, all reported using EC syndrome value 0x07:

  • FPCR, FPSR, FPEXC32_EL2, any of the SIMD and floating-point registers V0-V31, including their views as D0-D31 registers or S0-31 registers. See 'The SIMD and floating-point registers, V0-V31' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
  • MVFR0, MVFR1, MVFR2, FPCSR, FPEXC, and any of the SIMD and floating-point registers Q0-15, including their views as D0-D31 registers or S0-31 registers. See 'Advanced SIMD and floating-point System registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Permitted VMSR accesses to FPSID are ignored, but for the purposes of this trap the architecture define a VMSR access to the FPSID from EL1 or higher as an access to a SIMD and floating-point register.

TFPMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at any Exception level to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPTR_EL3.EZ.

Note

FPEXC32_EL2 is not accessible from EL0 using AArch64.

FPSID, MRFR0, MVFR1, and FPEXC are not accessible from EL0 using AArch32.

This field resets to an architecturally UNKNOWN value.

Bit [9]

Reserved, RES0.

EZ, bit [8]

When SVE is implemented:

Traps all accesses to SVE functionality and registers from all Exception levels, and both Security states, to EL3.

EZMeaning
0b0

This control causes these instructions executed at any Exception level to be trapped, subject to the exception prioritization rules.

0b1

This control does not cause any instruction to be trapped.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [7:0]

Reserved, RES0.

Accessing the CPTR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, CPTR_EL3

op0op1CRnCRmop2
0b110b1100b00010b00010b010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    return CPTR_EL3;
              

MSR CPTR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00010b010
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    CPTR_EL3 = X[t];
              


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