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DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 15

The DBGBVR<n>_EL1 characteristics are:

Purpose

Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1.

Configuration

AArch64 System register DBGBVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBVR<n>[31:0] .

AArch64 System register DBGBVR<n>_EL1 bits [63:32] are architecturally mapped to AArch32 System register DBGBXVR<n>[31:0] .

AArch64 System register DBGBVR<n>_EL1 bits [63:0] are architecturally mapped to External register DBGBVR<n>_EL1[63:0] .

If breakpoint n is not implemented then accesses to this register are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

How this register is interpreted depends on the value of DBGBCR<n>_EL1.BT.

  • When DBGBCR<n>_EL1.BT is 0b000x, this register holds a virtual address.
  • When DBGBCR<n>_EL1.BT is 0b001x, 0b011x, or 0b110x, this register holds a Context ID.
  • When DBGBCR<n>_EL1.BT is 0b100x, this register holds a VMID.
  • When DBGBCR<n>_EL1.BT is 0b101x, this register holds a VMID and a Context ID.
  • When DBGBCR<n>_EL1.BT is 0b111x, this register holds two Context ID values.

For other values of DBGBCR<n>_EL1.BT, this register is RES0.

Field descriptions

The DBGBVR<n>_EL1 bit assignments are:

When DBGBCR<n>_EL1.BT == 0b000x:
6362616059585756555453525150494847464544434241403938373635343332
RESS[14:4]VA[52:49]VA[48:2]
VA[48:2]RES0

RESS[14:4], bits [63:53]

Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.

It is IMPLEMENTATION DEFINED whether:

  • Reads return the value of the most significant bit of the VA for every bit in this field.
  • Reads return the last value written.

The PE ignores this field.

VA[52:49], bits [52:49]

When ARMv8.2-LVA is implemented:

Extension to VA[48:2]. See VA[48:2] for more details.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Extension to RESS[14:4]. See RESS[14:4] for more details.

VA[48:2], bits [48:2]

Bits[48:2] of the address value for comparison.

When ARMv8.2-LVA is implemented, VA[52:49] forms the upper part of the address value. Otherwise, VA[52:49] are RESS.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

Bits [1:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT == 0b001x:
6362616059585756555453525150494847464544434241403938373635343332
RES0
ContextID

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison.

The value is compared against CONTEXTIDR_EL2 when ARMv8.1-VHE is implemented, HCR_EL2.E2H is 1, and either:

  • The PE is executing at EL2.
  • HCR_EL2.TGE is 1, the PE is executing at EL0, and EL2 is enabled in the current Security state.

Otherwise, the value is compared against CONTEXTIDR_EL1.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

When DBGBCR<n>_EL1.BT == 0b011x:
6362616059585756555453525150494847464544434241403938373635343332
RES0
ContextID

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

When DBGBCR<n>_EL1.BT == 0b100x and HaveEL(EL2):
6362616059585756555453525150494847464544434241403938373635343332
RES0VMID[15:8]VMID[7:0]
RES0

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]

When ARMv8.1-VMID16 is implemented:

Extension to VMID[7:0]. See VMID[7:0] for more details.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits in the following cases.

  • EL2 is using AArch32.
  • ARMv8.1-VMID16 is not implemented.

When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.

VMID[15:8] is RES0 if any of the following applies:

  • The implementation has an 8-bit VMID.
  • VTCR_EL2.VS has a value of 0.
  • EL2 is using AArch32.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT == 0b101x and HaveEL(EL2):
6362616059585756555453525150494847464544434241403938373635343332
RES0VMID[15:8]VMID[7:0]
ContextID

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]

When ARMv8.1-VMID16 is implemented:

Extension to VMID[7:0]. See VMID[7:0] for more details.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits in the following cases.

  • EL2 is using AArch32.
  • ARMv8.1-VMID16 is not implemented.

When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.

VMID[15:8] is RES0 if any of the following applies:

  • The implementation has an 8-bit VMID.
  • VTCR_EL2.VS has a value of 0.
  • EL2 is using AArch32.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

When DBGBCR<n>_EL1.BT == 0b110x and HaveEL(EL2):
6362616059585756555453525150494847464544434241403938373635343332
ContextID2
RES0

ContextID2, bits [63:32]

When ARMv8.1-VHE is implemented:

Context ID value for comparison against CONTEXTIDR_EL2.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT == 0b111x, HaveEL(EL2) and ARMv8.1-VHE is implemented:
6362616059585756555453525150494847464544434241403938373635343332
ContextID2
ContextID
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210
313029282726252423222120191817161514131211109876543210

ContextID2, bits [63:32]

When ARMv8.1-VHE is implemented:

Context ID value for comparison against CONTEXTIDR_EL2.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

The following resets apply:

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

  • On a Warm reset, the value of this field is unchanged.

Accessing the DBGBVR<n>_EL1

Accesses to this register use the following encodings:

MRS <Xt>, DBGBVR<n>_EL1

op0op1CRnCRmop2
0b100b0000b0000n[3:0]0b100
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.DBGBVRn_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        return DBGBVR_EL1[UInt(CRm<3:0>)];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        return DBGBVR_EL1[UInt(CRm<3:0>)];
elsif PSTATE.EL == EL3 then
    if !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        return DBGBVR_EL1[UInt(CRm<3:0>)];
              

MSR DBGBVR<n>_EL1, <Xt>

op0op1CRnCRmop2
0b100b0000b0000n[3:0]0b100
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.DBGBVRn_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        DBGBVR_EL1[UInt(CRm<3:0>)] = X[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        DBGBVR_EL1[UInt(CRm<3:0>)] = X[t];
elsif PSTATE.EL == EL3 then
    if !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        DBGBVR_EL1[UInt(CRm<3:0>)] = X[t];
              


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