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ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0

The ID_AA64DFR0_EL1 characteristics are:

Purpose

Provides top level information about the debug system in AArch64 state.

For general information about the interpretation of the ID registers, see Principles of the ID scheme for fields in ID registers.

Configuration

The external register EDDFR gives information from this register.

Attributes

ID_AA64DFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64DFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0MTPMURES0TraceFiltDoubleLockPMSVer
CTX_CMPsRES0WRPsRES0BRPsPMUVerTraceVerDebugVer
313029282726252423222120191817161514131211109876543210

Bits [63:52]

Reserved, RES0.

MTPMU, bits [51:48]

Multi-threaded PMU extension. Defined values are:

MTPMUMeaning
0b0000

FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, it is IMPLEMENTATION DEFINED whether PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are read/write or RES0.

0b0001

FEAT_MTPMU and FEAT_PMUv3 implemented. PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are read/write. When FEAT_MTPMU is disabled, the Effective values of PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are 0.

0b1111

FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, PMEVTYPER<n>_EL0.MT and PMEVTYPER<n>.MT are RES0.

All other values are reserved.

FEAT_MTPMU implements the functionality identified by the value 0b0001.

From Armv8.6, in an implementation that includes FEAT_PMUv3, the value 0b0000 is not permitted.

In an implementation that does not include FEAT_PMUv3, the value 0b0001 is not permitted.

Bits [47:44]

Reserved, RES0.

TraceFilt, bits [43:40]

Armv8.4 Self-hosted Trace Extension version. Defined values are:

TraceFiltMeaning
0b0000

Armv8.4 Self-hosted Trace Extension not implemented.

0b0001

Armv8.4 Self-hosted Trace Extension implemented.

All other values are reserved.

FEAT_TRF implements the functionality identified by the value 0b0001.

From Armv8.4, if an Embedded Trace Macrocell Architecture PE Trace Unit is implemented, the value 0b0000 is not permitted.

DoubleLock, bits [39:36]

OS Double Lock implemented. Defined values are:

DoubleLockMeaning
0b0000

OS Double Lock implemented. OSDLR_EL1 is RW.

0b1111

OS Double Lock not implemented. OSDLR_EL1 is RAZ/WI.

All other values are reserved.

FEAT_DoubleLock implements the functionality identified by the value 0b0000.

In Armv8.0, the only permitted value is 0b0000.

If FEAT_Debugv8p2 is implemented and FEAT_DoPD is not implemented, the permitted values are 0b0000 and 0b1111.

If FEAT_DoPD is implemented, the only permitted value is 0b1111.

PMSVer, bits [35:32]

Statistical Profiling Extension version. Defined values are:

PMSVerMeaning
0b0000

Statistical Profiling Extension not implemented.

0b0001

Statistical Profiling Extension implemented.

0b0010

As 0b0001, and adds:

  • Support for the Event packet Alignment flag.
  • If FEAT_SVE is implemented, support for the Scalable Vector extensions to Statistical Profiling.
0b0011

As 0b0010, and adds:

  • The last branch target Address packet.
  • Discard mode.
  • Extended event filtering, including the PMSNEVFR_EL1 System register.
  • If FEAT_PMUv3 is implemented, controls to freeze the PMU event counters after an SPE buffer management event occurs.
  • If FEAT_PMUv3 is implemented, the SAMPLE_FEED_BR, SAMPLE_FEED_EVENT, SAMPLE_FEED_LAT, SAMPLE_FEED_LD, SAMPLE_FEED_OP, and SAMPLE_FEED_ST PMU events.

All other values are reserved.

FEAT_SPE implements the functionality identified by the value 0b0001.

FEAT_SPEv1p1 implements the functionality identified by the value 0b0010.

FEAT_SPEv1p2 implements the functionality identified by the value 0b0011.

In Armv8.5, if FEAT_SPE is implemented, the value 0b0001 is not permitted.

From Armv8.7, if FEAT_SPE is implemented, the value 0b0010 is not permitted.

CTX_CMPs, bits [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

Bits [27:24]

Reserved, RES0.

WRPs, bits [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

Bits [19:16]

Reserved, RES0.

BRPs, bits [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

PMUVer, bits [11:8]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version'

Defined values are:

PMUVerMeaning
0b0000

Performance Monitors Extension not implemented.

0b0001

Performance Monitors Extension, PMUv3 implemented.

0b0100

PMUv3 for Armv8.1. As 0b0001, and also includes support for:

0b0101

PMUv3 for Armv8.4. As 0b0100, and also includes support for the PMMIR_EL1 register.

0b0110

PMUv3 for Armv8.5. As 0b0101, and also includes support for:

  • 64-bit event counters.
  • If EL2 is implemented, the MDCR_EL2.HCCD control bit.
  • If EL3 is implemented, the MDCR_EL3.SCCD control bit.
0b0111

PMUv3 for Armv8.7. As 0b0110, and also includes support for:

  • The PMCR_EL0.FZO and, if EL2 is implemented, MDCR_EL2.HPMFZO control bits.
  • If EL3 is implemented, the MDCR_EL3.{MPMX,MCCD} control bits.
0b1111

IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations.

All other values are reserved.

FEAT_PMUv3 implements the functionality identified by the value 0b0001.

FEAT_PMUv3p1 implements the functionality identified by the value 0b0100.

FEAT_PMUv3p4 implements the functionality identified by the value 0b0101.

FEAT_PMUv3p5 implements the functionality identified by the value 0b0110.

FEAT_PMUv3p7 implements the functionality identified by the value 0b0111.

In Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001 is not permitted.

In Armv8.4, if FEAT_PMUv3 is implemented, the value 0b0100 is not permitted.

In Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted.

From Armv8.7, if FEAT_PMUv3 is implemented, the value 0b0110 is not permitted.

TraceVer, bits [7:4]

Trace support. Indicates whether System register interface to a PE trace unit is implemented. Defined values are:

TraceVerMeaning
0b0000

PE trace unit System registers not implemented.

0b0001

PE trace unit System registers implemented.

All other values are reserved.

See the ETM Architecture Specification for more information.

A value of 0b0000 only indicates that no System register interface to a PE trace unit is implemented. A PE trace unit might nevertheless be implemented without a System register interface.

DebugVer, bits [3:0]

Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:

DebugVerMeaning
0b0110

Armv8 debug architecture.

0b0111

Armv8 debug architecture with Virtualization Host Extensions.

0b1000

Armv8.2 debug architecture.

0b1001

Armv8.4 debug architecture.

All other values are reserved.

FEAT_Debugv8p2 adds the functionality identified by the value 0b1000.

FEAT_Debugv8p4 adds the functionality identified by the value 0b1001.

In Armv8.1, the value 0b0110 is not permitted.

In Armv8.2, the value 0b0111 is not permitted.

From Armv8.4, the value 0b1000 is not permitted.

Accessing the ID_AA64DFR0_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64DFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b01010b000
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64DFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64DFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64DFR0_EL1;