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ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0

The ID_AA64MMFR0_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch64 state.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

There are no configuration notes.

Attributes

ID_AA64MMFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64MMFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ECVFGTRES0ExSTGran4_2TGran64_2TGran16_2
TGran4TGran64TGran16BigEndEL0SNSMemBigEndASIDBitsPARange
313029282726252423222120191817161514131211109876543210

ECV, bits [63:60]

Indicates presence of Enhanced Counter Virtualization. Defined values are:

ECVMeaning
0b0000

Enhanced Counter Virtualization is not implemented.

0b0001

Enhanced Counter Virtualization is implemented. Supports CNTHCTL_EL2.{EL1TVT, EL1TVCT, EL1NVPCT, EL1NVVCT, EVNTIS}, CNTKCTL_EL1.EVNTIS, CNTPCTSS_EL0 counter views, and CNTVCTSS_EL0 counter views. Extends the PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS, and TRFCR_EL2.TS fields.

0b0010

As 0b0001, and also includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2.

All other values are reserved.

FEAT_ECV implements the functionality identified by the values 0b0001 and 0b0010.

From Armv8.6, the only permitted values are 0b0001 and 0b0010.

FGT, bits [59:56]

Indicates presence of the Fine-Grained Trap controls:

Defined values are:

FGTMeaning
0b0000

The fine-grained trap controls are not implemented.

0b0001

The fine-grained trap controls are implemented.

All other values are reserved.

FEAT_FGT implements the functionality identified by the value 0b0001.

From Armv8.6, the only permitted value is 0b0001.

Bits [55:48]

Reserved, RES0.

ExS, bits [47:44]

Indicates support for disabling context synchronizing exception entry and exit. Defined values are:

ExSMeaning
0b0000

All exception entries and exits are context synchronization events.

0b0001

Non-context synchronizing exception entry and exit are supported.

All other values are reserved.

FEAT_ExS implements the functionality identified by the value 0b0001.

TGran4_2, bits [43:40]

Indicates support for 4KB memory granule size at stage 2. Defined values are:

TGran4_2MeaningApplies when
0b0000

Support for 4KB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field.

0b0001

4KB granule not supported at stage 2.

0b0010

4KB granule supported at stage 2.

0b0011

4KB granule at stage 2 supports 52-bit input and output addresses.

When FEAT_LPA2 is implemented

All other values are reserved.

The 0b0000 value is deprecated.

TGran64_2, bits [39:36]

Indicates support for 64KB memory granule size at stage 2. Defined values are:

TGran64_2Meaning
0b0000

Support for 64KB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field.

0b0001

64KB granule not supported at stage 2.

0b0010

64KB granule supported at stage 2.

All other values are reserved.

The 0b0000 value is deprecated.

TGran16_2, bits [35:32]

Indicates support for 16KB memory granule size at stage 2. Defined values are:

TGran16_2MeaningApplies when
0b0000

Support for 16KB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field.

0b0001

16KB granule not supported at stage 2.

0b0010

16KB granule supported at stage 2.

0b0011

16KB granule at stage 2 supports 52-bit input and output addresses.

When FEAT_LPA2 is implemented

All other values are reserved.

The 0b0000 value is deprecated.

TGran4, bits [31:28]

Indicates support for 4KB memory translation granule size. Defined values are:

TGran4MeaningApplies when
0b0000

4KB granule supported.

0b0001

4KB granule supports 52-bit input and output addresses.

When FEAT_LPA2 is implemented
0b1111

4KB granule not supported.

All other values are reserved.

TGran64, bits [27:24]

Indicates support for 64KB memory translation granule size. Defined values are:

TGran64Meaning
0b0000

64KB granule supported.

0b1111

64KB granule not supported.

All other values are reserved.

TGran16, bits [23:20]

Indicates support for 16KB memory translation granule size. Defined values are:

TGran16MeaningApplies when
0b0000

16KB granule not supported.

0b0001

16KB granule supported.

0b0010

16KB granule supports 52-bit input and output addresses.

When FEAT_LPA2 is implemented

All other values are reserved.

BigEndEL0, bits [19:16]

Indicates support for mixed-endian at EL0 only. Defined values are:

BigEndEL0Meaning
0b0000

No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value.

0b0001

Mixed-endian support at EL0. The SCTLR_EL1.E0E bit can be configured.

All other values are reserved.

This field is invalid and is RES0 if ID_AA64MMFR0_EL1.BigEnd is not 0b0000.

SNSMem, bits [15:12]

Indicates support for a distinction between Secure and Non-secure Memory. Defined values are:

SNSMemMeaning
0b0000

Does not support a distinction between Secure and Non-secure Memory.

0b0001

Does support a distinction between Secure and Non-secure Memory.

Note

If EL3 is implemented, the value 0b0000 is not permitted.

All other values are reserved.

BigEnd, bits [11:8]

Indicates support for mixed-endian configuration. Defined values are:

BigEndMeaning
0b0000

No mixed-endian support. The 'SCTLR_ELx'.EE bits have a fixed value. See the BigEndEL0 field, bits[19:16], for whether EL0 supports mixed-endian.

0b0001

Mixed-endian support. The 'SCTLR_ELx'.EE and SCTLR_EL1.E0E bits can be configured.

All other values are reserved.

ASIDBits, bits [7:4]

Number of ASID bits. Defined values are:

ASIDBitsMeaning
0b0000

8 bits.

0b0010

16 bits.

All other values are reserved.

PARange, bits [3:0]

Physical Address range supported. Defined values are:

PARangeMeaning
0b0000

32 bits, 4GB.

0b0001

36 bits, 64GB.

0b0010

40 bits, 1TB.

0b0011

42 bits, 4TB.

0b0100

44 bits, 16TB.

0b0101

48 bits, 256TB.

0b0110

52 bits, 4PB.

All other values are reserved.

The value 0b0110 is permitted only if the implementation includes FEAT_LPA, otherwise it is reserved.

Accessing the ID_AA64MMFR0_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64MMFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b01110b000
if PSTATE.EL == EL0 then
    if IsFeatureImplemented(FEAT_IDST) then
        if EL2Enabled() && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64MMFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64MMFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64MMFR0_EL1;