ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

The ID_AA64PFR0_EL1 characteristics are:

Purpose

Provides additional information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

The external register EDPFR gives information from this register.

Attributes

ID_AA64PFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64PFR0_EL1 bit assignments are:

CSV3, bits [63:60]

From Armv8.5:

Speculative use of faulting data. Defined values are:

From Armv8.5, the only permitted value is 0b0001.

All other values are reserved.

Otherwise:

Reserved, RES0.

CSV2, bits [59:56]

From Armv8.5:

Speculative use of out of context branch targets. Defined values are:

From Armv8.5 the only permitted values are 0b0001 or 0b0010.

All other values are reserved.

Otherwise:

Reserved, RES0.

Bits [55:52]

Reserved, RES0.

DIT, bits [51:48]

From Armv8.4:

Data Independent Timing. Defined values are:

All other values are reserved.

ARMv8.4-DIT implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

Otherwise:

Reserved, RES0.

AMU, bits [47:44]

From Armv8.4:

Activity Monitors Extension. Defined values are:

All other values are reserved.

AMUv1 implements the functionality identified by the value 0b0001.

ARMv8.6-AMU implements the functionality identified by the value 0b0010.

Otherwise:

Reserved, RES0.

MPAM, bits [43:40]

From Armv8.2:

MPAM Extension. Defined values are:

All other values are reserved.

Otherwise:

Reserved, RES0.

SEL2, bits [39:36]

From Armv8.4:

Secure EL2. Defined values are:

All other values are reserved.

Otherwise:

Reserved, RES0.

SVE, bits [35:32]

From Armv8.2:

Scalable Vector Extension. Defined values are:

All other values are reserved.

If implemented, refer to ID_AA64ZFR0_EL1 for information about which SVE instructions are available.

Otherwise:

Reserved, RES0.

RAS, bits [31:28]

RAS Extension version. The defined values of this field are:

All other values are reserved.

From Armv8.4, when ARMv8.4-DFE is not implemented, and ERRIDR_EL1.NUM is zero, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010. Otherwise from Armv8.4 the only permitted value is 0b0010.

ARMv8.4-RAS implements the functionality identified by the value 0b0010.

In Armv8.2, the only permitted value is 0b0001.

In Armv8.1 and Armv8.0, the permitted values are 0b0000 and 0b0001.

GIC, bits [27:24]

System register GIC interface support. Defined values are:

All other values are reserved.

AdvSIMD, bits [23:20]

Advanced SIMD. Defined values are:

All other values are reserved.

This field must have the same value as the FP field.

The permitted values are:

• 0b0000 in an implementation with Advanced SIMD support that does not include the ARMv8.2-FP16 extension.
• 0b0001 in an implementation with Advanced SIMD support that includes the ARMv8.2-FP16 extension.
• 0b1111 in an implementation without Advanced SIMD support.

FP, bits [19:16]

Floating-point. Defined values are:

All other values are reserved.

This field must have the same value as the AdvSIMD field.

The permitted values are:

• 0b0000 in an implementation with floating-point support that does not include the ARMv8.2-FP16 extension.
• 0b0001 in an implementation with floating-point support that includes the ARMv8.2-FP16 extension.
• 0b1111 in an implementation without floating-point support.

EL3, bits [15:12]

EL3 Exception level handling. Defined values are:

All other values are reserved.

EL2, bits [11:8]

EL2 Exception level handling. Defined values are:

All other values are reserved.

EL1, bits [7:4]

EL1 Exception level handling. Defined values are:

All other values are reserved.

EL0, bits [3:0]

EL0 Exception level handling. Defined values are:

All other values are reserved.

if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64PFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64PFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64PFR0_EL1;