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ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1

The ID_AA64PFR1_EL1 characteristics are:

Purpose

Reserved for future expansion of information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

Attributes

ID_AA64PFR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64PFR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0RAS_fracMTESSBSBT
313029282726252423222120191817161514131211109876543210

Bits [63:16]

Reserved, RES0.

RAS_frac, bits [15:12]

When ARMv8.4-RAS is implemented:

RAS Extension fractional field.

RAS_fracMeaning
0b0000

If ID_AA64PFR0_EL1.RAS == 0b0001, RAS Extension implemented.

0b0001

If ID_AA64PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for:

Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.

All other values are reserved.

This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.


Otherwise:

Reserved, RES0.

MTE, bits [11:8]

When ARMv8.5-MemTag is implemented:

Support for the Tagged Memory Extension.

MTEMeaning
0b0000

Tagged Memory Extension is not implemented.

0b0001

Tagged Memory Instructions accessible at EL0 are implemented. Instructions and System Registers defined by the extension not configurably accessible at EL0 are Unallocated and other System Register fields defined by the extension are RES0.

0b0010

Tagged Memory Extension is implemented.

When only Memory Tagging Extension Instructions accessible at EL0 are implemented:

All other values are reserved.


Otherwise:

Reserved, RES0.

SSBS, bits [7:4]

From Armv8.5:

Speculative Store Bypassing controls in AArch64 state. Defined values are:

SSBSMeaning
0b0000

AArch64 provides no mechanism to control the use of Speculative Store Bypassing.

0b0001

AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe.

0b0010

AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe, and the MSR and MRS instructions to directly read and write the PSTATE.SSBS field

All other values are reserved.


Otherwise:

Reserved, RES0.

BT, bits [3:0]

From Armv8.5:

Branch Target Identification mechanism support in AArch64 state. Defined values are:

BTMeaning
0b0000

The Branch Target Identification mechanism is not implemented.

0b0001

The Branch Target Identification mechanism is implemented.

All other values are reserved.

ARMv8.5-BTI implements the functionality identified by the value 0b0001.

From Armv8.5, the only permitted value is 0b0001.


Otherwise:

Reserved, RES0.

Accessing the ID_AA64PFR1_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64PFR1_EL1

op0op1CRnCRmop2
0b110b0000b00000b01000b001
if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64PFR1_EL1;
              


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