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ID_AA64ZFR0_EL1, SVE Feature ID register 0

The ID_AA64ZFR0_EL1 characteristics are:

Purpose

Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.

For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers.

Configuration

This register is present only when SVE is implemented. Otherwise, direct accesses to ID_AA64ZFR0_EL1 are RAZ.

Attributes

ID_AA64ZFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64ZFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0F64MMF32MMRES0I8MMRES0
RES0BF16RES0SVEver
313029282726252423222120191817161514131211109876543210

Bits [63:60]

Reserved, RES0.

F64MM, bits [59:56]

From Armv8.2:

Indicates support for SVE FP64 double-precision floating-point matrix multiplication instructions. Defined values are:

F64MMMeaning
0b0000

FP64 matrix multiplication and related instructions are not implemented.

0b0001

FMMLA, and LD1RO* instructions are implemented. The 128-bit element variations of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 are also implemented.

All other values are reserved.

ARMv8.2-F64MM implements the functionality identified by 0b0001.


Otherwise:

Reserved, RES0.

F32MM, bits [55:52]

From Armv8.2:

Indicates support for the SVE FP32 single-precision floating-point matrix multiplication instruction. Defined values are:

F32MMMeaning
0b0000

FP32 matrix multiplication instruction is not implemented.

0b0001

FMMLA instruction is implemented.

All other values are reserved.

ARMv8.2-F32MM implements the functionality identified by 0b0001.


Otherwise:

Reserved, RES0.

Bits [51:48]

Reserved, RES0.

I8MM, bits [47:44]

From Armv8.2:

Indicates support for SVE Int8 matrix multiplication instructions. Defined values are:

I8MMMeaning
0b0000

Int8 matrix multiplication instructions are not implemented.

0b0001

SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.

All other values are reserved.

ARMv8.2-I8MM implements the functionality identified by 0b0001.

From Armv8.6, the only permitted value is 0b0001.


Otherwise:

Reserved, RES0.

Bits [43:24]

Reserved, RES0.

BF16, bits [23:20]

From Armv8.2:

Indicates support for SVE BFloat16 instructions. Defined values are:

BF16Meaning
0b0000

BFloat16 instructions are not implemented.

0b0001

BFCVT, BFCVTNT, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented.

All other values are reserved.

ARMv8.2-BF16 implements the functionality identified by 0b0001.

From ARMv8.6, the only permitted value is 0b0001.


Otherwise:

Reserved, RES0.

Bits [19:4]

Reserved, RES0.

SVEver, bits [3:0]

Scalable Vector Extension instruction set version. Defined values are:

SVEverMeaning
0b0000

SVE instructions are implemented.

All other values are reserved. This field is only valid if the ID_AA64PFR0_EL1.SVE field is not zero.

Accessing the ID_AA64ZFR0_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64ZFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b01000b100
if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_AA64ZFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_AA64ZFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_AA64ZFR0_EL1;
              


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