ID_PFR0_EL1, AArch32 Processor Feature Register 0

The ID_PFR0_EL1 characteristics are:

Purpose

Gives top-level information about the instruction sets supported by the PE in AArch32 state.

Must be interpreted with ID_PFR1_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

AArch64 System register ID_PFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR0[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_PFR0_EL1 is a 64-bit register.

Field descriptions

The ID_PFR0_EL1 bit assignments are:

Bits [63:32]

Reserved, RES0.

RAS, bits [31:28]

RAS Extension version.

All other values are reserved.

From Armv8.4, when ARMv8.4-DFE is not implemented, and ERRIDR.NUM is zero, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010. Otherwise from Armv8.4 the only permitted value is 0b0010.

ARMv8.4-RAS implements the functionality identified by the value 0b0010.

In Armv8.2, the only permitted value is 0b0001.

In Armv8.1 and Armv8.0, the permitted values are 0b0000 and 0b0001.

DIT, bits [27:24]

From Armv8.4:

Data Independent Timing. Defined values are:

All other values are reserved.

ARMv8.4-DIT implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

Otherwise:

Reserved, RES0.

AMU, bits [23:20]

From Armv8.4:

Activity Monitors Extension. Defined values are:

All other values are reserved.

AMUv1 implements the functionality identified by the value 0b0001.

ARMv8.6-AMU implements the functionality identified by the value 0b0010.

Otherwise:

Reserved, RES0.

CSV2, bits [19:16]

From Armv8.5:

Speculative use of out of context branch targets. Defined values are:

From Armv8.5 the only permitted value is 0b0001.

All other values are reserved.

Otherwise:

Reserved, RES0.

State3, bits [15:12]

T32EE instruction set support. Defined values are:

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

State2, bits [11:8]

Jazelle extension support. Defined values are:

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

State1, bits [7:4]

T32 instruction set support. Defined values are:

All other values are reserved.

In Armv8-A the only permitted value is 0b0011.

State0, bits [3:0]

A32 instruction set support. Defined values are:

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

if PSTATE.EL == EL0 then
    if IsFeatureImplemented("ARMv8.4-IDST") then
        if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        return ID_PFR0_EL1;
elsif PSTATE.EL == EL2 then
    return ID_PFR0_EL1;
elsif PSTATE.EL == EL3 then
    return ID_PFR0_EL1;