ID_PFR0_EL1, AArch32 Processor Feature Register 0
The ID_PFR0_EL1 characteristics are:
Purpose
Gives top-level information about the instruction sets supported by the PE in AArch32 state.
Must be interpreted with ID_PFR1_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register ID_PFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR0[31:0] .
Attributes
ID_PFR0_EL1 is a 64-bit register.
Field descriptions
The ID_PFR0_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:32]
Reserved, RES0.
RAS, bits [31:28]
RAS Extension version. Defined values are:
RAS | Meaning |
---|---|
0b0000 |
No RAS Extension. |
0b0001 |
RAS Extension present. |
0b0010 | FEAT_RASv1p1 present. As 0b0001, and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. |
All other values are reserved.
FEAT_RAS implements the functionality identified by the value 0b0001.
FEAT_RASv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0 and Armv8.1, the permitted values are 0b0000 and 0b0001.
In Armv8.2, the only permitted value is 0b0001.
From Armv8.4, if FEAT_DoubleFault is implemented, the only permitted value is 0b0010.
From Armv8.4, when FEAT_DoubleFault is not implemented, and ERRIDR_EL1.NUM is 0, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010.
When the value of this field is 0b0001, ID_PFR2_EL1.RAS_frac indicates whether FEAT_RASv1p1 is implemented.
DIT, bits [27:24]
Data Independent Timing. Defined values are:
DIT | Meaning |
---|---|
0b0000 |
AArch32 does not guarantee constant execution time of any instructions. |
0b0001 |
AArch32 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions. |
All other values are reserved.
FEAT_DIT implements the functionality identified by the value 0b0001.
From Armv8.4, the only permitted value is 0b0001.
AMU, bits [23:20]
Indicates support for Activity Monitors Extension. Defined values are:
AMU | Meaning |
---|---|
0b0000 |
Activity Monitors Extension is not implemented. |
0b0001 |
FEAT_AMUv1 is implemented. |
0b0010 |
FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. |
All other values are reserved.
FEAT_AMUv1 implements the functionality identified by the value 0b0001.
FEAT_AMUv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0, the only permitted value is 0b0000.
In Armv8.4, the permitted values are 0b0000 and 0b0001.
From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010.
CSV2, bits [19:16]
Speculative use of out of context branch targets. Defined values are:
CSV2 | Meaning |
---|---|
0b0000 |
This Device does not disclose whether branch targets trained in one hardware described context can affect speculative execution in a different hardware described context. |
0b0001 |
Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. |
All other values are reserved.
FEAT_CSV2 implements the functionality identified by 0b0001.
From Armv8.5, the only permitted value is 0b0001.
State3, bits [15:12]
T32EE instruction set support. Defined values are:
State3 | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
T32EE instruction set implemented. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
State2, bits [11:8]
Jazelle extension support. Defined values are:
State2 | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. |
0b0010 |
Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
State1, bits [7:4]
T32 instruction set support. Defined values are:
State1 | Meaning |
---|---|
0b0000 |
T32 instruction set not implemented. |
0b0001 | T32 encodings before the introduction of Thumb-2 technology implemented:
|
0b0011 |
T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0011.
State0, bits [3:0]
A32 instruction set support. Defined values are:
State0 | Meaning |
---|---|
0b0000 |
A32 instruction set not implemented. |
0b0001 |
A32 instruction set implemented. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the ID_PFR0_EL1
Accesses to this register use the following encodings:
MRS <Xt>, ID_PFR0_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_PFR0_EL1; elsif PSTATE.EL == EL2 then return ID_PFR0_EL1; elsif PSTATE.EL == EL3 then return ID_PFR0_EL1;