MPAM3_EL3, MPAM3 Register (EL3)
The MPAM3_EL3 characteristics are:
Purpose
Holds information to generate MPAM labels for memory requests when executing at EL3.
Configuration
AArch64 System register MPAM3_EL3 bit [63] is architecturally mapped to AArch64 System register MPAM2_EL2[63] when HaveEL(EL2).
AArch64 System register MPAM3_EL3 bit [63] is architecturally mapped to AArch64 System register MPAM1_EL1[63] .
This register is present only when MPAM is implemented. Otherwise, direct accesses to MPAM3_EL3 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
Attributes
MPAM3_EL3 is a 64-bit register.
Field descriptions
The MPAM3_EL3 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| MPAMEN | TRAPLOWER | RES0 | PMG_D | PMG_I | |||||||||||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPAMEN, bit [63]
MPAM Enable: MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
Values of this field are:
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information when executing at any ELn. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. |
This field is always read/write in MPAM3_EL3.
This field resets to 0.
TRAPLOWER, bit [62]
Trap direct accesses to any MPAM system registers that are not UNDEFINED from all ELn lower than EL3.
| TRAPLOWER | Meaning |
|---|---|
| 0b0 |
Do not force trapping of direct accesses of MPAM system registers to EL3. |
| 0b1 |
Force all direct accesses of MPAM system registers to trap to EL3. |
On a Cold reset, this field resets to 1.
Bits [61:48]
Reserved, RES0.
PMG_D, bits [47:40]
Performance monitoring group for data accesses.
This field resets to an architecturally UNKNOWN value.
PMG_I, bits [39:32]
Performance monitoring group for instruction accesses.
PARTID_D, bits [31:16]
Partition ID for data accesses, including load and store accesses, made from EL3.
This field resets to an architecturally UNKNOWN value.
PARTID_I, bits [15:0]
Partition ID for instruction accesses made from EL3.
This field resets to an architecturally UNKNOWN value.
Accessing the MPAM3_EL3
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings:
MRS <Xt>, MPAM3_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
return MPAM3_EL3;
MSR MPAM3_EL3, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b1010 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
MPAM3_EL3 = X[t];