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ZCR_EL3, SVE Control Register for EL3

The ZCR_EL3 characteristics are:

Purpose

The SVE Control Register for EL3 is used to control aspects of SVE visible at all Exception levels.

Configuration

This register is present only when SVE is implemented. Otherwise, direct accesses to ZCR_EL3 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

ZCR_EL3 is a 64-bit register.

Field descriptions

The ZCR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0RAZ/WILEN
313029282726252423222120191817161514131211109876543210

Bits [63:9]

Reserved, RES0.

Bits [8:4]

Reserved, RAZ/WI.

LEN, bits [3:0]

Constrains the scalable vector register length for all Exception levels to (LEN+1)x128 bits. For all purposes other than returning the result of a direct read of ZCR_EL3 then this field behaves as if rounded down to the nearest implemented vector length.

An indirect read of ZCR_EL3.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.

This field resets to an architecturally UNKNOWN value.

Accessing the ZCR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, ZCR_EL3

op0op1CRnCRmop2
0b110b1100b00010b00100b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.EZ == '0' then
        AArch64.SystemAccessTrap(EL3, 0x19);
    else
        return ZCR_EL3;
              

MSR ZCR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00100b000
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.EZ == '0' then
        AArch64.SystemAccessTrap(EL3, 0x19);
    else
        ZCR_EL3 = X[t];
              


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