You copied the Doc URL to your clipboard.

AMCIDR1, Activity Monitors Component Identification Register 1

The AMCIDR1 characteristics are:

Purpose

Provides information to identify an activity monitors component.

For more information, see About the Component identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Configuration

The power domain of AMCIDR1 is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCIDR1 are RES0.

Attributes

AMCIDR1 is a 32-bit register.

Field descriptions

The AMCIDR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0CLASSPRMBL_1

Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class. Reads as 0x9, CoreSight component.

PRMBL_1, bits [3:0]

Preamble. Reads as 0x0.

Accessing the AMCIDR1

AMCIDR1 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xFF4AMCIDR1

Accesses on this interface are RO.



Was this page helpful? Yes No