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AMDEVARCH, Activity Monitors Device Architecture Register

The AMDEVARCH characteristics are:

Purpose

Identifies the programmers' model architecture of the AMU component.

Configuration

The power domain of AMDEVARCH is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMDEVARCH are RES0.

Attributes

AMDEVARCH is a 32-bit register.

Field descriptions

The AMDEVARCH bit assignments are:

313029282726252423222120191817161514131211109876543210
ARCHITECTPRESENTREVISIONARCHID

ARCHITECT, bits [31:21]

Defines the architecture of the component. For AMU, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0x4.

Bits [27:21] are the JEP106 ID code, 0x3B.

PRESENT, bit [20]

When set to 1, indicates that the DEVARCH is present.

This field is 1 in Armv8.

REVISION, bits [19:16]

Defines the architecture revision. For architectures defined by Arm this is the minor revision.

REVISIONMeaning
0b0000

Architecture revision is AMUv1.

All other values are reserved.

ARCHID, bits [15:0]

Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.

For AMU:

  • Bits [15:12] are the architecture version, 0x0.
  • Bits [11:0] are the architecture part number, 0xA66.

This corresponds to AMU architecture version AMUv1.

Accessing the AMDEVARCH

AMDEVARCH can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xFBCAMDEVARCH

Accesses on this interface are RO.



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