CNTFID0, Counter Frequency ID
The CNTFID0 characteristics are:
Indicates the base frequency of the system counter.
The power domain of CNTFID0 is IMPLEMENTATION DEFINED.
If this register is implemented as an RW register, on a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The possible frequencies for the system counter are stored in the Frequency modes table as 32-bit words starting with the base frequency, CNTFID0. For more information see 'The Frequency modes table' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The final entry in the Frequency modes table must be followed by a 32-bit word of zero value, to mark the end of the table.
Typically, the Frequency modes table will be in read-only memory. However, a system implementation might use read/write memory for the table, and initialize the table entries as part of its start-up sequence.
If the Frequency modes table is in read/write memory, Arm strongly recommends that the table is not updated once the system is running.
CNTFID0 is a 32-bit register.
The CNTFID0 bit assignments are:
Frequency, bits [31:0]
The base frequency of the system counter, in Hz.
This field resets to an architecturally UNKNOWN value.
Accessing the CNTFID0
It is IMPLEMENTATION DEFINED whether this register is RO or RW
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
CNTFID0 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO or RW.