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EDCIDSR, External Debug Context ID Sample Register

The EDCIDSR characteristics are:


Contains the sampled value of the Context ID, captured on reading EDPCSR[31:0].


EDCIDSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.


ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.


EDCIDSR is a 32-bit register.

Field descriptions

The EDCIDSR bit assignments are:

When ARMv8.2-PCSample is implemented:

Bits [31:0]

Reserved, RES0.


CONTEXTIDR, bits [31:0]

Context ID. The value of CONTEXTIDR that is associated with the most recent EDPCSR sample.

  • If EL1 is using AArch64, then the Context ID is held in CONTEXTIDR_EL1.
  • If EL1 is using AArch32, then the Context ID is held in CONTEXTIDR.
  • If EL3 is implemented and is using AArch32, then CONTEXTIDR is a banked register, and EDCIDSR samples the current banked copy of CONTEXTIDR for the Security state that is associated with the most recent EDPCSR sample.

Because the value written to EDCIDSR is an indirect read of CONTEXTIDR, therefore it is CONSTRAINED UNPREDICTABLE whether EDCIDSR is set to the original or new value if a read of EDPCSRlo samples:

  • An instruction that writes to CONTEXTIDR_EL1.
  • The next Context synchronization event.
  • Any instruction executed between these two instructions.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the EDCIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in chapter H7.

EDCIDSR can be accessed through the external debug interface:


This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.

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