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ERRCIDR1, Component Identification Register 1

The ERRCIDR1 characteristics are:

Purpose

Provides discovery information for the component.

Configuration

Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRCIDR1 are RES0.

Attributes

ERRCIDR1 is a 32-bit register.

Field descriptions

The ERRCIDR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0CLASSPRMBL_1

Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class.

CLASSMeaning
0b1111

Generic peripheral with IMPLEMENTATION DEFINED register layout.

This field reads as 0xF.

Other values are defined by the CoreSight Architecture.

PRMBL_1, bits [3:0]

Component identification preamble, segment 1. This field reads as 0x0.

Accessing the ERRCIDR1

ERRCIDR1 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xFF4ERRCIDR1

Accesses on this interface are RO.



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