You copied the Doc URL to your clipboard.

ERRERICR1, Error Recovery Interrupt Configuration Register 1

The ERRERICR1 characteristics are:

Purpose

Interrupt configuration register.

Configuration

External register ERRERICR1 bits [31:0] are architecturally mapped to External register ERRIRQCR3[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRERICR1 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

Attributes

ERRERICR1 is a 32-bit register.

Field descriptions

The ERRERICR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
DATA

DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

  • On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERRERICR1

ERRERICR1 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xE98ERRERICR1

Accesses on this interface are RW.



Was this page helpful? Yes No