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ERR<n>CTLR, Error Record Control Register, n = 0 - 65534

The ERR<n>CTLR characteristics are:

Purpose

The error control register contains enable bits for the node that writes to this record, which:

  • Enable error detection and correction.

  • Enable an error recovery interrupt.

  • Enable a fault handling interrupt.

  • Enable error recovery reporting as a read or write error response.

  • When ARMv.4-RAS is implemented, enable a critical error interrupt.

For each bit, if the selected node does not support the feature, then the bit is RES0. The definition of each record is IMPLEMENTATION DEFINED.

Configuration

Some or all RW fields of this register have defined reset values.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, or error record <n> is not the first error record owned by the node, ERR<n>CTLR is RES0.

ERR<n>FR describes the features implemented by the node.

Attributes

ERR<n>CTLR is a 64-bit register.

Field descriptions

The ERR<n>CTLR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
RES0CIRES0WDUIDUIWCFICFIWUEWFIWUIUEFIUIIMPLEMENTATION DEFINEDED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:32]

IMPLEMENTATION DEFINED.

Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.

This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

Bits [31:14]

Reserved, RES0.

CI, bit [13]

When ERR<n>FR.CI == 0b10:

Critical error interrupt enable.

When enabled, the critical error interrupt is generated for a critical error condition.

CIMeaning
0b0

Critical error interrupt not generated for critical errors. Critical errors are treated as Uncontained errors.

0b1

Critical error interrupt generated for critical errors.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bit [12]

Reserved, RES0.

WDUI, bit [11]

When ERR<n>FR.DUI == 0b11:

Error recovery interrupt for deferred errors on writes enable.

When enabled, the error recovery interrupt is generated for all detected Deferred errors on writes.

WDUIMeaning
0b0

Error recovery interrupt not generated for deferred errors on writes.

0b1

Error recovery interrupt generated for deferred errors on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

DUI, bit [10]

When ERR<n>FR.DUI == 0b10:

Error recovery interrupt for deferred errors enable. This control applies to errors arising from both reads and writes.

When enabled, an error recovery interrupt is generated for all detected Deferred errors.

DUIMeaning
0b0

Error recovery interrupt not generated for deferred errors.

0b1

Error recovery interrupt generated for deferred errors.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


When ERR<n>FR.DUI == 0b11:

When ERR<n>FR.DUI == 0b11, this field is named RDUI.

Error recovery interrupt for deferred errors on reads enable.

When enabled, the error recovery interrupt is generated for all detected Deferred errors on reads.

RDUIMeaning
0b0

Error recovery interrupt not generated for deferred errors on reads.

0b1

Error recovery interrupt generated for deferred errors on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

WCFI, bit [9]

When ERR<n>FR.CFI == 0b11:

Fault handling interrupt for Corrected errors on writes enable.

When enabled:

  • If the node implements Corrected error counters, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 1. For more information, see ERR<n>MISC0.
  • Otherwise, the fault handling interrupt is also generated for all detected Corrected errors on writes.
WCFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors on writes.

0b1

Fault handling interrupt generated for Corrected errors on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

CFI, bit [8]

When ERR<n>FR.CFI == 0b10:

Fault handling interrupt for Corrected errors enable. This control applies to errors arising from both reads and writes.

When enabled:

  • If the node implements Corrected error counters, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 1. For more information, see ERR<n>MISC0.
  • Otherwise, the fault handling interrupt is generated for all detected Corrected errors.
CFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors.

0b1

Fault handling interrupt generated for Corrected errors.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


When ERR<n>FR.CFI == 0b11:

When ERR<n>FR.CFI == 0b11, this field is named RCFI.

Fault handling interrupt for Corrected errors on reads enable.

When enabled:

  • If the node implements Corrected error counters, then the fault handling interrupt is generated when a counter overflows and the overflow bit for the counter is set to 1. For more information, see ERR<n>MISC0.
  • Otherwise, the fault handling interrupt is generated for all detected Corrected errors on reads.
RCFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors on reads.

0b1

Fault handling interrupt generated for Corrected errors on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

WUE, bit [7]

When ERR<n>FR.UE == 0b11:

In-band Uncorrected error reporting on writes enable.

When enabled, responses to writes that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).

WUEMeaning
0b0

External abort response for Uncorrected errors disabled for writes.

0b1

External abort response for Uncorrected errors enabled for writes.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

WFI, bit [6]

When ERR<n>FR.FI == 0b11:

Fault handling interrupt on writes enable.

When enabled:

  • The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors on writes.
  • If the fault handling interrupt for Corrected errors control is not implemented:
    • If the node implements Corrected error counters, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 1.
    • Otherwise, the fault handling interrupt is also generated for all detected Corrected errors on writes.
WFIMeaning
0b0

Fault handling interrupt disabled on writes.

0b1

Fault handling interrupt enabled on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

WUI, bit [5]

When ERR<n>FR.UI == 0b11:

Uncorrected error recovery interrupt on writes enable.

When enabled, the error recovery interrupt is generated for all detected Uncorrected errors on writes that are not deferred.

WUIMeaning
0b0

Error recovery interrupt disabled on writes.

0b1

Error recovery interrupt enabled on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

UE, bit [4]

When ERR<n>FR.UE == 0b10:

In-band Uncorrected error reporting enable.

When enabled, responses to transactions that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).

UEMeaning
0b0

External abort response for Uncorrected errors disabled.

0b1

External abort response for Uncorrected errors enabled.

Note

This control applies to errors arising from both reads and writes.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


When ERR<n>FR.UE == 0b11:

When ERR<n>FR.UE == 0b11, this field is named RUE.

In-band Uncorrected error reporting on reads enable.

When enabled, responses to reads that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).

RUEMeaning
0b0

External abort response for Uncorrected errors disabled for reads.

0b1

External abort response for Uncorrected errors enabled for reads.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

FI, bit [3]

When ERR<n>FR.FI == 0b10:

Fault handling interrupt enable. This control applies to errors arising from both reads and writes.

When enabled:

  • The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors.
  • If the fault handling interrupt for Corrected errors control is not implemented:
    • If the node implements Corrected error counters, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 1.
    • Otherwise, the fault handling interrupt is also generated for all detected Corrected errors.
FIMeaning
0b0

Fault handling interrupt disabled.

0b1

Fault handling interrupt enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


When ERR<n>FR.FI == 0b11:

When ERR<n>FR.FI == 0b11, this field is named RFI.

Fault handling interrupt on reads enable.

When enabled:

  • The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors on reads.
  • If the fault handling interrupt for Corrected errors control is not implemented:
    • If the node implements Corrected error counters, then the fault handling interrupt is also generated when a counter overflows and the overflow bit for the counter is set to 1.
    • Otherwise, the fault handling interrupt is also generated for all detected Corrected errors on reads.
RFIMeaning
0b0

Fault handling interrupt disabled on reads.

0b1

Fault handling interrupt enabled on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

UI, bit [2]

When ERR<n>FR.UI == 0b10:

Uncorrected error recovery interrupt enable. This control applies to errors arising from both reads and writes.

When enabled, the error recovery interrupt is generated for all detected Uncorrected errors that are not deferred.

UIMeaning
0b0

Error recovery interrupt disabled.

0b1

Error recovery interrupt enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


When ERR<n>FR.UI == 0b11:

When ERR<n>FR.UI == 0b11, this field is named RUI.

Uncorrected error recovery interrupt on reads enable.

When enabled, the error recovery interrupt is generated for all detected Uncorrected errors on reads that are not deferred.

RUIMeaning
0b0

Error recovery interrupt disabled on reads.

0b1

Error recovery interrupt enabled on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

IMPLEMENTATION DEFINED, bit [1]

IMPLEMENTATION DEFINED.

Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.

This bit reads as an IMPLEMENTATION DEFINED value and writes to this bit have IMPLEMENTATION DEFINED behavior.

ED, bit [0]

When ERR<n>FR.ED == 0b10:

Error reporting and logging enable.

When disabled, the node behaves as if error detection and correction are disabled, and no errors are recorded or signaled by the node. Arm recommends that, when disabled, correct error detection and correction codes are written for writes, unless disabled by an IMPLEMENTATION DEFINED control for error injection.

EDMeaning
0b0

Error reporting disabled.

0b1

Error reporting enabled.

It is IMPLEMENTATION DEFINED whether the node fully disables error detection and correction when reporting is disabled. That is, even with error reporting disabled, the node might continue to silently correct errors. Uncorrectable errors might result in corrupt data being silently propagated by the node.

Note

If this node requires initialization after Cold reset to prevent signaling false errors, then Arm recommends this bit is set to 0 on Cold reset. This allows boot software to initialize a node without signaling errors. Software can enable error reporting after the node is initialized. If the Cold reset value is 1, the reset values of other controls in this register are IMPLEMENTATION DEFINED and should not be UNKNOWN.

The following resets apply:

  • This bit is preserved on an Error Recovery reset.

  • On a Cold reset, this field resets to an IMPLEMENTATION DEFINED value.


Otherwise:

Reserved, RES0.

Accessing the ERR<n>CTLR

ERR<n>CTLR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x008 + 64nERR<n>CTLR

Accesses on this interface are RW.



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