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GICC_DIR, CPU Interface Deactivate Interrupt Register

The GICC_DIR characteristics are:

Purpose

When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt.

Configuration

Attributes

GICC_DIR is a 32-bit register.

Field descriptions

The GICC_DIR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the signaled interrupt.

Note

INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.

When affinity routing is not enabled:

  • Bits [23:13] are RES0.
  • For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.

Accessing the GICC_DIR

This register is used only when System register access is not enabled. When System register access is enabled:

  • For AArch32 implementations, ICC_DIR provides equivalent functionality.
  • For AArch64 implementations, ICC_DIR_EL1 provides equivalent functionality.

Writes to this register have an effect only in the following cases:

  • When GICD_CTLR.DS == 1, if GICC_CTLR.EOImode == 1.
  • In GIC implementations that support two Security states:
    • If the access is Secure and GICC_CTLR.EOImodeS == 1.
    • If the access is Non-secure and GICC_CTLR.EOImodeNS == 1.

The following writes must be ignored:

  • Writes to this register when the corresponding EOImode field in GICC_CTLR == 0. In systems that support system error generation, an implementation might generate a system error.
  • Writes to this register when the corresponding EOImode field in GICC_CTLR == 0 and the corresponding interrupt is not active. In systems that support system error generation, an implementation might generate a system error. In implementations using the GIC Stream Protocol Interface these writes correspond to a Deactivate packet for an interrupt that is not active.

If the corresponding EOImode field in GICC_CTLR is 1 and this register is written to without a corresponding write to GICC_EOIR or GICC_AEOIR, the interrupt is deactivated but the bit corresponding to it in the active priorities registers remains set.

When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.

GICC_DIR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC CPU interface0x1000GICC_DIR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are WO.
  • When IsAccessSecure() accesses to this register are WO.
  • When !IsAccessSecure() accesses to this register are WO.


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