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GICC_NSAPR<n>, CPU Interface Non-secure Active Priorities Registers, n = 0 - 3

The GICC_NSAPR<n> characteristics are:

Purpose

Provides information about Group 1 interrupt active priorities.

Configuration

Some or all RW fields of this register have defined reset values.

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses.

GICC_NSAPR1 is only implemented in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are only implemented in implementations that support 7 bits of priority.

Attributes

GICC_NSAPR<n> is a 32-bit register.

Field descriptions

The GICC_NSAPR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

This field resets to 0.

Accessing the GICC_NSAPR<n>

GICC_NSAPR<n> can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC CPU interface0x00E0 + 4nGICC_NSAPR<n>

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are RW.
  • When IsAccessSecure() accesses to this register are RW.
  • When !IsAccessSecure() accesses to this register are RW.


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