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GICC_STATUSR, CPU Interface Status Register

The GICC_STATUSR characteristics are:

Purpose

Provides software with a mechanism to detect:

  • Accesses to reserved locations.
  • Writes to read-only locations.
  • Reads of write-only locations.

Configuration

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions.

Attributes

GICC_STATUSR is a 32-bit register.

Field descriptions

The GICC_STATUSR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0ASVWRODRWODWRDRRD

Bits [31:5]

Reserved, RES0.

ASV, bit [4]

Attempted security violation.

ASVMeaning
0b0

Normal operation.

0b1

A Non-secure access to a Secure register has been detected.

Note

This bit is not set to 1 for registers where any of the fields are Non-secure.

WROD, bit [3]

Write to an RO location.

WRODMeaning
0b0

Normal operation.

0b1

A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RWOD, bit [2]

Read of a WO location.

RWODMeaning
0b0

Normal operation.

0b1

A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

WRD, bit [1]

Write to a reserved location.

WRDMeaning
0b0

Normal operation.

0b1

A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RRD, bit [0]

Read of a reserved location.

RRDMeaning
0b0

Normal operation.

0b1

A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

Accessing the GICC_STATUSR

This is an optional register. If the register is not implemented, the location is RAZ/WI.

If this register is implemented, GICV_STATUSR must also be implemented.

GICC_STATUSR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC CPU interface0x002CGICC_STATUSR (S)

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are RW.
  • When IsAccessSecure() accesses to this register are RW.
ComponentOffsetInstance
GIC CPU interface0x002CGICC_STATUSR (NS)

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are RW.
  • When !IsAccessSecure() accesses to this register are RW.


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