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GICD_IGROUPR<n>E, Interrupt Group Registers (extended SPI range), n = 0 - 31

The GICD_IGROUPR<n>E characteristics are:

Purpose

Controls whether the corresponding SPI in the extended SPI range is in Group 0 or Group 1.

Configuration

GICD_IGROUPR<n>E resets to 0x00000000.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1:

  • The number of implemented GICD_IGROUPR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
  • When GICD_CLTR.DS==0, this register is Secure.

Attributes

GICD_IGROUPR<n>E is a 32-bit register.

Field descriptions

The GICD_IGROUPR<n>E bit assignments are:

313029282726252423222120191817161514131211109876543210
Group_status_bit<x>, bit [x], for x = 0 to 31

Group_status_bit<x>, bit [x], for x = 0 to 31

Group status bit.

Group_status_bit<x>Meaning
0b0

When GICD_CTLR.DS==1, the corresponding interrupt is Group 0.

When GICD_CTLR.DS==0, the corresponding interrupt is Secure.

0b1

When GICD_CTLR.DS==1, the corresponding interrupt is Group 1.

When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.

If affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGRPMODR<n>E to form a 2-bit field that defines an interrupt group. The encoding of this field is described in GICD_IGRPMODR<n>E.

If affinity routing is disabled for the Security state of an interrupt, the bit is RES0:

For INTID m, when DIV and MOD are the integer division and modulo operations:

  • The corresponding GICD_IGROUPR<n>E number, n, is given by n = (m-4096) DIV 32.
  • The offset of the required GICD_IGROUPR<n>E is (0x1000 + (4*n)).
  • The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

Accessing the GICD_IGROUPR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICD_IGROUPR<n>E can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Distributor0x1000 + 4nGICD_IGROUPR<n>E

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are RW.
  • When IsAccessSecure() accesses to this register are RW.
  • When !IsAccessSecure() accesses to this register are RW.


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