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GICD_SGIR, Software Generated Interrupt Register

The GICD_SGIR characteristics are:

Purpose

Controls the generation of SGIs.

Configuration

This register is available in all configurations of the GIC. If the GIC supports two Security states this register is Common.

Attributes

GICD_SGIR is a 32-bit register.

Field descriptions

The GICD_SGIR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0TargetListFilterCPUTargetListNSATTRES0INTID

Bits [31:26]

Reserved, RES0.

TargetListFilter, bits [25:24]

Determines how the Distributor processes the requested SGI.

TargetListFilterMeaning
0b00

Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList.

0b01

Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt.

0b10

Forward the interrupt only to the CPU interface of the PE that requested the interrupt.

0b11

Reserved.

CPUTargetList, bits [23:16]

When GICD_SGIR.TargetListFilter is 0b00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.

Each bit of the field refers to the corresponding CPU interface. For example, CPUTargetList[0] corresponds to interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface.

If this field is 0b00000000 when GICD_SGIR.TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface.

NSATT, bit [15]

Specifies the required group of the SGI.

NSATTMeaning
0b0

Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface.

0b1

Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 1 on that interface.

This field is writable only by a Secure access. Non-secure accesses can also generate Group 0 interrupts, if allowed to do so by GICD_NSACR0. Otherwise, Non-secure writes to GICD_SGIR generate an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit [15] of the write.

Bits [14:4]

Reserved, RES0.

INTID, bits [3:0]

The INTID of the SGI to forward to the specified CPU interfaces.

Accessing the GICD_SGIR

This register is used only when affinity routing is not enabled. When affinity routing is enabled, this register is RES0.

It is IMPLEMENTATION DEFINED whether this register has any effect when the forwarding of interrupts by the Distributor is disabled by GICD_CTLR.

GICD_SGIR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Distributor0x0F00GICD_SGIR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are WO.
  • When IsAccessSecure() accesses to this register are WO.
  • When !IsAccessSecure() accesses to this register are WO.


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