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GICR_ISACTIVER0, Interrupt Set-Active Register 0

The GICR_ISACTIVER0 characteristics are:

Purpose

Activates the corresponding SGI or PPI. These registers are used when saving and restoring GIC state.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISACTIVER0 is a 32-bit register.

Field descriptions

The GICR_ISACTIVER0 bit assignments are:

313029282726252423222120191817161514131211109876543210
Set_active_bit<x>, bit [x], for x = 0 to 31

Set_active_bit<x>, bit [x], for x = 0 to 31

Adds the active state to interrupt number x. Reads and writes have the following behavior:

Set_active_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not active, and is not active and pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is active, or is active and pending.

If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect.

After a write of 1 to this bit, a subsequent read of this bit returns 1.

This field resets to an architecturally UNKNOWN value.

Accessing the GICR_ISACTIVER0

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISACTIVER0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ISACTIVER<n> with n=0.

This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ISACTIVER<n>.

When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.

GICR_ISACTIVER0 can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0300GICR_ISACTIVER0

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are RW.
  • When IsAccessSecure() accesses to this register are RW.
  • When !IsAccessSecure() accesses to this register are RW.


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