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PMCID2SR, CONTEXTIDR_EL2 Sample Register

The PMCID2SR characteristics are:

Purpose

Contains the sampled value of CONTEXTIDR_EL2, captured on reading PMPCSR[31:0].

Configuration

PMCID2SR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

This register is present only when ARMv8.2-PCSample is implemented. Otherwise, direct accesses to PMCID2SR are RES0.

Note

Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.

If EL2 is not implemented, this register is RES0.

Attributes

PMCID2SR is a 32-bit register.

Field descriptions

The PMCID2SR bit assignments are:

313029282726252423222120191817161514131211109876543210
CONTEXTIDR_EL2

CONTEXTIDR_EL2, bits [31:0]

Context ID. The value of CONTEXTIDR that is associated with the most recent PMPCSR sample.

  • If EL2 is using AArch64, then the Context ID sampled from CONTEXTIDR_EL2.
  • If EL2 is using AArch32, then this field is set to an UNKNOWN value.

Because the value written to PMCID2SR is an indirect read of CONTEXTIDR, therefore it is CONSTRAINED UNPREDICTABLE whether PMCID2SR is set to the original or new value if a read of PMPCSR samples:

  • An instruction that writes to CONTEXTIDR_EL2.
  • The next Context synchronization event.
  • Any instruction executed between these two instructions.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the PMCID2SR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile

PMCID2SR can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0x22CPMCID2SR

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.


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