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PMITCTRL, Performance Monitors Integration mode Control register

The PMITCTRL characteristics are:

Purpose

Enables the Performance Monitors to switch from default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.

Configuration

It is IMPLEMENTATION DEFINED whether PMITCTRL is implemented in the Core power domain or in the Debug power domain. Some or all RW fields of this register have defined reset values, and:

  • The register is not affected by a Warm reset.
  • If the register is implemented in the Core power domain the reset values apply on a Cold reset, and the register is not affected by an External debug reset.
  • If the register is implemented in the Debug power domain the reset values apply on an External debug reset, and the register is not affected by a Cold reset.

Implementation of this register is OPTIONAL.

Attributes

PMITCTRL is a 32-bit register.

Field descriptions

The PMITCTRL bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0IME

Bits [31:1]

Reserved, RES0.

IME, bit [0]

Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED.

IMEMeaning
0b0

Normal operation.

0b1

Integration mode enabled.

On a Implementation reset, this field resets to 0.

Accessing the PMITCTRL

PMITCTRL can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xF00PMITCTRL

This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
  • When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
  • Otherwise accesses to this register are IMPDEF.


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