PMMIR, Performance Monitors Machine Identification Register
The PMMIR characteristics are:
Describes Performance Monitors parameters specific to the implementation.
PMMIR is in the Core power domain.
This register is present only when ARMv8.4-PMU is implemented. Otherwise, direct accesses to PMMIR are RES0.
PMMIR is a 32-bit register.
The PMMIR bit assignments are:
SLOTS, bits [7:0]
Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is implemented, this field must not be zero.
Accessing the PMMIR
If the Core power domain is off or in a low-power state, access on this interface returns an Error.
PMMIR can be accessed through the external debug interface:
This interface is accessible as follows:
- When !IsCorePowered(), or DoubleLockStatus(), or OSLockStatus() or !AllowExternalPMUAccess() accesses to this register generate an error response.
- Otherwise accesses to this register are RO.