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## FRECPX

Floating-point reciprocal exponent (predicated).

Invert the exponent leaving the fractional part unchanged of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

The result of this instruction can be used with FMULX to convert arbitrary elements in mathematical vector space to "unit vectors" or "direction vectors" of length 1.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 size 0 0 1 1 0 0 1 0 1 Pg Zn Zd

#### SVE

FRECPX <Zd>.<T>, <Pg>/M, <Zn>.<T>

```if !HaveSVE() then UNDEFINED;
if size == '00' then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer n = UInt(Zn);
integer d = UInt(Zd);```

### Assembler Symbols

 Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D
 Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 Is the name of the source scalable vector register, encoded in the "Zn" field.

### Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand = Z[n];
bits(VL) result = Z[d];

for e = 0 to elements-1
bits(esize) element = Elem[operand, e, esize];
if ElemP[mask, e, esize] == '1' then
Elem[result, e, esize] = FPRecpX(element, FPCR);

Z[d] = result;```