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Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).



ISB {<option>|#<imm>}

MemBarrierOp op;
MBReqDomain domain;
MBReqTypes types;

op = MemBarrierOp_ISB;
case CRm<3:2> of
    when '00' domain = MBReqDomain_OuterShareable;
    when '01' domain = MBReqDomain_Nonshareable;
    when '10' domain = MBReqDomain_InnerShareable;
    when '11' domain = MBReqDomain_FullSystem;

case CRm<1:0> of
    when '01' types = MBReqTypes_Reads;
    when '10' types = MBReqTypes_Writes;
    when '11' types = MBReqTypes_All;
        if CRm<3:2> == '01' then
            op = MemBarrierOp_PSSBB;
        elsif HaveSBExt() && FALSE then
            op = MemBarrierOp_SB;
            types = MBReqTypes_All;
            domain = MBReqDomain_FullSystem;

Assembler Symbols


Specifies an optional limitation on the barrier operation. Values are:

Full system barrier operation, encoded as CRm = 0b1111. Can be omitted.

All other encodings of CRm are reserved. The corresponding instructions execute as full system barrier operations, but must not be relied upon by software.


Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field.

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