LDCLR, LDCLRA, LDCLRAL, LDCLRL
Atomic bit clear on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.
- If the destination register is not one of WZR or XZR, LDCLRA and LDCLRAL load from memory with acquire semantics.
- LDCLRL and LDCLRAL store to memory with release semantics.
- LDCLR has no memory ordering requirements.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
This instruction is used by the alias STCLR, STCLRL.
if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; boolean tag_checked = n != 31;
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
|Alias||Is preferred when|
|STCLR, STCLRL||A == '0' && Rt == '11111'|
bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); value = X[s]; if n == 31 then CheckSPAlignment(); address = SP; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = Mem[address, datasize DIV 8, ldacctype]; result = data AND NOT(value); Mem[address, datasize DIV 8, stacctype] = result; if t != 31 then X[t] = ZeroExtend(data, regsize);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.