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Load Tag Vector loads an implementation defined number of Allocation Tags from the naturally aligned array of 16 Allocation Tags which includes a tag whose address is the address in the source register, and writes them to the destination register. Bits of the destination register which do not store a tag are set to 0. The Allocation Tag at the address in the source register is always loaded, and the first source register is updated to the address of the first Allocation Tag at an address higher than the original address that was not loaded.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.




LDGV <Xt>, [<Xn|SP>]!

integer t = UInt(Xt);
integer n = UInt(Xn);
boolean wback = TRUE;
boolean wb_unknown = FALSE;

Assembler Symbols


Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.


Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.


bits(64) data = Zeros(64);
bits(64) address;
integer count;

if n == t then
    c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
    assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};

    case c of
        when Constraint_WBSUPPRESS wback = FALSE;    // writeback is suppressed
        when Constraint_UNKNOWN    wb_unknown = TRUE;    // writeback is UNKNOWN
        when Constraint_UNDEF      UnallocatedEncoding();
        when Constraint_NOP        EndOfInstruction();

if n == 31 then
    address = SP[];
    address = X[n];

(address, count) = ImpDefTagArrayStartAndCount(address);

for i = 0 to count-1
    integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>);
    bits(4) tag = MemTag[address];
    data<(index*4)+3:(index*4)> = tag;
    address = address + TAG_GRANULE;

X[t] = data;

if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    if n == 31 then
        SP[] = address;
        X[n] = address;
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