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Store Tag Vector reads from the second source register an implementation defined number of Allocation Tags and stores them to the naturally aligned array of 16 allocation tags which includes a tag whose address is the address in the first source register. The Allocation Tag at the address in the first source register is always stored, and the first source register is updated to the address of the first Allocation Tag at an address higher than the original address that was not loaded.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.




STGV <Xt>, [<Xn|SP>]!

integer t = UInt(Xt);
integer n = UInt(Xn);

Assembler Symbols


Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.


Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.


bits(64) data = X[t];
bits(64) address;

if n == 31 then
    address = SP[];
    address = X[n];

// address<63:LOG2_TAG_GRANULE+4>:Zeros(LOG2_TAG_GRANULE+4) <= start <= address
// 0 < count <= 16-start<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
integer count;
(address, count) = ImpDefTagArrayStartAndCount(address);

for i = 0 to count-1
    integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>);
    bits(4) tag = data<(index*4)+3:index*4>;
    MemTag[address] = tag;
    address = address + TAG_GRANULE;

if n == 31 then
    SP[] = address;
    X[n] = address;