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Data Processing -- Scalar Floating-Point and Advanced SIMD

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 111 op1 op2 op3
Decode fields Instruction details Architecture version
op0 op1 op2 op3
0000 0x x101 00xxxxx10 UNALLOCATED -
0010 0x x101 00xxxxx10 UNALLOCATED -
0100 0x x101 00xxxxx10 Cryptographic AES -
0101 0x x0xx xxx0xxx00 Cryptographic three-register SHA -
0101 0x x0xx xxx0xxx10 UNALLOCATED -
0101 0x x101 00xxxxx10 Cryptographic two-register SHA -
0110 0x x101 00xxxxx10 UNALLOCATED -
0111 0x x0xx xxx0xxxx0 UNALLOCATED -
0111 0x x101 00xxxxx10 UNALLOCATED -
01x1 00 00xx xxx0xxxx1 Advanced SIMD scalar copy -
01x1 01 00xx xxx0xxxx1 UNALLOCATED -
01x1 0x 0111 00xxxxx10 UNALLOCATED -
01x1 0x 10xx xxx00xxx1 Advanced SIMD scalar three same FP16 Armv8.2
01x1 0x 10xx xxx01xxx1 UNALLOCATED -
01x1 0x 1111 00xxxxx10 Advanced SIMD scalar two-register miscellaneous FP16 Armv8.2
01x1 0x x0xx xxx1xxxx0 UNALLOCATED -
01x1 0x x0xx xxx1xxxx1 Advanced SIMD scalar three same extra Armv8.1
01x1 0x x100 00xxxxx10 Advanced SIMD scalar two-register miscellaneous -
01x1 0x x110 00xxxxx10 Advanced SIMD scalar pairwise Armv8.2
01x1 0x x1xx 1xxxxxx10 UNALLOCATED -
01x1 0x x1xx x1xxxxx10 UNALLOCATED -
01x1 0x x1xx xxxxxxx00 Advanced SIMD scalar three different -
01x1 0x x1xx xxxxxxxx1 Advanced SIMD scalar three same -
01x1 10 xxxxxxxx1 Advanced SIMD scalar shift by immediate -
01x1 11 xxxxxxxx1 UNALLOCATED -
01x1 1x xxxxxxxx0 Advanced SIMD scalar x indexed element Armv8.2
0x00 0x x0xx xxx0xxx00 Advanced SIMD table lookup -
0x00 0x x0xx xxx0xxx10 Advanced SIMD permute -
0x10 0x x0xx xxx0xxxx0 Advanced SIMD extract -
0xx0 00 00xx xxx0xxxx1 Advanced SIMD copy -
0xx0 01 00xx xxx0xxxx1 UNALLOCATED -
0xx0 0x 0111 00xxxxx10 UNALLOCATED -
0xx0 0x 10xx xxx00xxx1 Advanced SIMD three same (FP16) Armv8.2
0xx0 0x 10xx xxx01xxx1 UNALLOCATED -
0xx0 0x 1111 00xxxxx10 Advanced SIMD two-register miscellaneous (FP16) Armv8.2
0xx0 0x x0xx xxx1xxxx0 UNALLOCATED -
0xx0 0x x0xx xxx1xxxx1 Advanced SIMD three same extra Armv8.2
0xx0 0x x100 00xxxxx10 Advanced SIMD two-register miscellaneous Armv8.5
0xx0 0x x110 00xxxxx10 Advanced SIMD across lanes Armv8.2
0xx0 0x x1xx 1xxxxxx10 UNALLOCATED -
0xx0 0x x1xx x1xxxxx10 UNALLOCATED -
0xx0 0x x1xx xxxxxxx00 Advanced SIMD three different -
0xx0 0x x1xx xxxxxxxx1 Advanced SIMD three same Armv8.2
0xx0 10 0000 xxxxxxxx1 Advanced SIMD modified immediate Armv8.2
0xx0 10 != 0000 xxxxxxxx1 Advanced SIMD shift by immediate -
0xx0 11 xxxxxxxx1 UNALLOCATED -
0xx0 1x xxxxxxxx0 Advanced SIMD vector x indexed element Armv8.2
1100 00 10xx xxx10xxxx Cryptographic three-register, imm2 Armv8.2
1100 00 11xx xxx1x00xx Cryptographic three-register SHA 512 Armv8.2
1100 00 xxx0xxxxx Cryptographic four-register Armv8.2
1100 01 00xx XAR Armv8.2
1100 01 1000 0001000xx Cryptographic two-register SHA 512 Armv8.2
1xx0 1x UNALLOCATED -
x0x1 0x x0xx Conversion between floating-point and fixed-point Armv8.2
x0x1 0x x1xx xxx000000 Conversion between floating-point and integer Armv8.3
x0x1 0x x1xx xxxx10000 Floating-point data-processing (1 source) Armv8.5
x0x1 0x x1xx xxxxx1000 Floating-point compare Armv8.2
x0x1 0x x1xx xxxxxx100 Floating-point immediate Armv8.2
x0x1 0x x1xx xxxxxxx01 Floating-point conditional compare Armv8.2
x0x1 0x x1xx xxxxxxx10 Floating-point data-processing (2 source) Armv8.2
x0x1 0x x1xx xxxxxxx11 Floating-point conditional select Armv8.2
x0x1 1x Floating-point data-processing (3 source) Armv8.2

Cryptographic AES

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 1 1 0 size 1 0 1 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details
size opcode
x1xxx UNALLOCATED
000xx UNALLOCATED
1xxxx UNALLOCATED
x1 UNALLOCATED
00 00100 AESE
00 00101 AESD
00 00110 AESMC
00 00111 AESIMC
1x UNALLOCATED

Cryptographic three-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 1 1 1 0 size 0 Rm 0 opcode 0 0 Rn Rd
Decode fields Instruction Details
size opcode
111 UNALLOCATED
x1 UNALLOCATED
00 000 SHA1C
00 001 SHA1P
00 010 SHA1M
00 011 SHA1SU0
00 100 SHA256H
00 101 SHA256H2
00 110 SHA256SU1
1x UNALLOCATED

Cryptographic two-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 1 1 1 0 size 1 0 1 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details
size opcode
xx1xx UNALLOCATED
x1xxx UNALLOCATED
1xxxx UNALLOCATED
x1 UNALLOCATED
00 00000 SHA1H
00 00001 SHA1SU1
00 00010 SHA256SU0
00 00011 UNALLOCATED
1x UNALLOCATED

Advanced SIMD scalar copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 op 1 1 1 1 0 0 0 0 imm5 0 imm4 1 Rn Rd
Decode fields Instruction Details
op imm5 imm4
0 xxx1 UNALLOCATED
0 xx1x UNALLOCATED
0 x1xx UNALLOCATED
0 0000 DUP (element)
0 1xxx UNALLOCATED
0 x0000 0000 UNALLOCATED
1 UNALLOCATED

Advanced SIMD scalar three same FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 a 1 0 Rm 0 0 opcode 1 Rn Rd
Decode fields Instruction Details Architecture Version
U a opcode
110 UNALLOCATED -
1 011 UNALLOCATED -
0 0 011 FMULX Armv8.2
0 0 100 FCMEQ (register) Armv8.2
0 0 101 UNALLOCATED -
0 0 111 FRECPS Armv8.2
0 1 100 UNALLOCATED -
0 1 101 UNALLOCATED -
0 1 111 FRSQRTS Armv8.2
1 0 011 UNALLOCATED -
1 0 100 FCMGE (register) Armv8.2
1 0 101 FACGE Armv8.2
1 0 111 UNALLOCATED -
1 1 010 FABD Armv8.2
1 1 100 FCMGT (register) Armv8.2
1 1 101 FACGT Armv8.2
1 1 111 UNALLOCATED -

Advanced SIMD scalar two-register miscellaneous FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 a 1 1 1 1 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
U a opcode
00xxx UNALLOCATED -
010xx UNALLOCATED -
10xxx UNALLOCATED -
1100x UNALLOCATED -
11110 UNALLOCATED -
0 011xx UNALLOCATED -
0 11111 UNALLOCATED -
1 01111 UNALLOCATED -
1 11100 UNALLOCATED -
0 0 11010 FCVTNS (vector) Armv8.2
0 0 11011 FCVTMS (vector) Armv8.2
0 0 11100 FCVTAS (vector) Armv8.2
0 0 11101 SCVTF (vector, integer) Armv8.2
0 1 01100 FCMGT (zero) Armv8.2
0 1 01101 FCMEQ (zero) Armv8.2
0 1 01110 FCMLT (zero) Armv8.2
0 1 11010 FCVTPS (vector) Armv8.2
0 1 11011 FCVTZS (vector, integer) Armv8.2
0 1 11101 FRECPE Armv8.2
0 1 11111 FRECPX Armv8.2
1 0 11010 FCVTNU (vector) Armv8.2
1 0 11011 FCVTMU (vector) Armv8.2
1 0 11100 FCVTAU (vector) Armv8.2
1 0 11101 UCVTF (vector, integer) Armv8.2
1 1 01100 FCMGE (zero) Armv8.2
1 1 01101 FCMLE (zero) Armv8.2
1 1 01110 UNALLOCATED -
1 1 11010 FCVTPU (vector) Armv8.2
1 1 11011 FCVTZU (vector, integer) Armv8.2
1 1 11101 FRSQRTE Armv8.2
1 1 11111 UNALLOCATED -

Advanced SIMD scalar three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 size 0 Rm 1 opcode 1 Rn Rd
Decode fields Instruction Details Architecture Version
U opcode
001x UNALLOCATED -
01xx UNALLOCATED -
1xxx UNALLOCATED -
0 0000 UNALLOCATED -
0 0001 UNALLOCATED -
1 0000 SQRDMLAH (vector) Armv8.1
1 0001 SQRDMLSH (vector) Armv8.1

Advanced SIMD scalar two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 size 1 0 0 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details
U size opcode
0000x UNALLOCATED
00010 UNALLOCATED
0010x UNALLOCATED
00110 UNALLOCATED
01111 UNALLOCATED
1000x UNALLOCATED
10011 UNALLOCATED
10101 UNALLOCATED
10111 UNALLOCATED
1100x UNALLOCATED
11110 UNALLOCATED
0x 011xx UNALLOCATED
0x 11111 UNALLOCATED
1x 10110 UNALLOCATED
1x 11100 UNALLOCATED
0 00011 SUQADD
0 00111 SQABS
0 01000 CMGT (zero)
0 01001 CMEQ (zero)
0 01010 CMLT (zero)
0 01011 ABS
0 10010 UNALLOCATED
0 10100 SQXTN, SQXTN2
0 0x 10110 UNALLOCATED
0 0x 11010 FCVTNS (vector)
0 0x 11011 FCVTMS (vector)
0 0x 11100 FCVTAS (vector)
0 0x 11101 SCVTF (vector, integer)
0 1x 01100 FCMGT (zero)
0 1x 01101 FCMEQ (zero)
0 1x 01110 FCMLT (zero)
0 1x 11010 FCVTPS (vector)
0 1x 11011 FCVTZS (vector, integer)
0 1x 11101 FRECPE
0 1x 11111 FRECPX
1 00011 USQADD
1 00111 SQNEG
1 01000 CMGE (zero)
1 01001 CMLE (zero)
1 01010 UNALLOCATED
1 01011 NEG (vector)
1 10010 SQXTUN, SQXTUN2
1 10100 UQXTN, UQXTN2
1 0x 10110 FCVTXN, FCVTXN2
1 0x 11010 FCVTNU (vector)
1 0x 11011 FCVTMU (vector)
1 0x 11100 FCVTAU (vector)
1 0x 11101 UCVTF (vector, integer)
1 1x 01100 FCMGE (zero)
1 1x 01101 FCMLE (zero)
1 1x 01110 UNALLOCATED
1 1x 11010 FCVTPU (vector)
1 1x 11011 FCVTZU (vector, integer)
1 1x 11101 FRSQRTE
1 1x 11111 UNALLOCATED

Advanced SIMD scalar pairwise

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 size 1 1 0 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
00xxx UNALLOCATED -
010xx UNALLOCATED -
01110 UNALLOCATED -
10xxx UNALLOCATED -
1100x UNALLOCATED -
11010 UNALLOCATED -
111xx UNALLOCATED -
1x 01101 UNALLOCATED -
0 11011 ADDP (scalar) -
0 00 01100 FMAXNMP (scalar)half-precision Armv8.2
0 00 01101 FADDP (scalar)half-precision Armv8.2
0 00 01111 FMAXP (scalar)half-precision Armv8.2
0 01 01100 UNALLOCATED -
0 01 01101 UNALLOCATED -
0 01 01111 UNALLOCATED -
0 10 01100 FMINNMP (scalar)half-precision Armv8.2
0 10 01111 FMINP (scalar)half-precision Armv8.2
0 11 01100 UNALLOCATED -
0 11 01111 UNALLOCATED -
1 11011 UNALLOCATED -
1 0x 01100 FMAXNMP (scalar)single-precision and double-precision -
1 0x 01101 FADDP (scalar)single-precision and double-precision -
1 0x 01111 FMAXP (scalar)single-precision and double-precision -
1 1x 01100 FMINNMP (scalar)single-precision and double-precision -
1 1x 01111 FMINP (scalar)single-precision and double-precision -

Advanced SIMD scalar three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 size 1 Rm opcode 0 0 Rn Rd
Decode fields Instruction Details
U opcode
00xx UNALLOCATED
01xx UNALLOCATED
1000 UNALLOCATED
1010 UNALLOCATED
1100 UNALLOCATED
111x UNALLOCATED
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 1101 UNALLOCATED

Advanced SIMD scalar three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 0 size 1 Rm opcode 1 Rn Rd
Decode fields Instruction Details
U size opcode
00000 UNALLOCATED
0001x UNALLOCATED
00100 UNALLOCATED
011xx UNALLOCATED
1001x UNALLOCATED
1x 11011 UNALLOCATED
0 00001 SQADD
0 00101 SQSUB
0 00110 CMGT (register)
0 00111 CMGE (register)
0 01000 SSHL
0 01001 SQSHL (register)
0 01010 SRSHL
0 01011 SQRSHL
0 10000 ADD (vector)
0 10001 CMTST
0 10100 UNALLOCATED
0 10101 UNALLOCATED
0 10110 SQDMULH (vector)
0 10111 UNALLOCATED
0 0x 11000 UNALLOCATED
0 0x 11001 UNALLOCATED
0 0x 11010 UNALLOCATED
0 0x 11011 FMULX
0 0x 11100 FCMEQ (register)
0 0x 11101 UNALLOCATED
0 0x 11110 UNALLOCATED
0 0x 11111 FRECPS
0 1x 11000 UNALLOCATED
0 1x 11001 UNALLOCATED
0 1x 11010 UNALLOCATED
0 1x 11100 UNALLOCATED
0 1x 11101 UNALLOCATED
0 1x 11110 UNALLOCATED
0 1x 11111 FRSQRTS
1 00001 UQADD
1 00101 UQSUB
1 00110 CMHI (register)
1 00111 CMHS (register)
1 01000 USHL
1 01001 UQSHL (register)
1 01010 URSHL
1 01011 UQRSHL
1 10000 SUB (vector)
1 10001 CMEQ (register)
1 10100 UNALLOCATED
1 10101 UNALLOCATED
1 10110 SQRDMULH (vector)
1 10111 UNALLOCATED
1 0x 11000 UNALLOCATED
1 0x 11001 UNALLOCATED
1 0x 11010 UNALLOCATED
1 0x 11011 UNALLOCATED
1 0x 11100 FCMGE (register)
1 0x 11101 FACGE
1 0x 11110 UNALLOCATED
1 0x 11111 UNALLOCATED
1 1x 11000 UNALLOCATED
1 1x 11001 UNALLOCATED
1 1x 11010 FABD
1 1x 11100 FCMGT (register)
1 1x 11101 FACGT
1 1x 11110 UNALLOCATED
1 1x 11111 UNALLOCATED

Advanced SIMD scalar shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 1 0 immh immb opcode 1 Rn Rd
Decode fields Instruction Details
U immh opcode
!= 0000 00001 UNALLOCATED
!= 0000 00011 UNALLOCATED
!= 0000 00101 UNALLOCATED
!= 0000 00111 UNALLOCATED
!= 0000 01001 UNALLOCATED
!= 0000 01011 UNALLOCATED
!= 0000 01101 UNALLOCATED
!= 0000 01111 UNALLOCATED
!= 0000 101xx UNALLOCATED
!= 0000 110xx UNALLOCATED
!= 0000 11101 UNALLOCATED
!= 0000 11110 UNALLOCATED
0000 UNALLOCATED
0 != 0000 00000 SSHR
0 != 0000 00010 SSRA
0 != 0000 00100 SRSHR
0 != 0000 00110 SRSRA
0 != 0000 01000 UNALLOCATED
0 != 0000 01010 SHL
0 != 0000 01100 UNALLOCATED
0 != 0000 01110 SQSHL (immediate)
0 != 0000 10000 UNALLOCATED
0 != 0000 10001 UNALLOCATED
0 != 0000 10010 SQSHRN, SQSHRN2
0 != 0000 10011 SQRSHRN, SQRSHRN2
0 != 0000 11100 SCVTF (vector, fixed-point)
0 != 0000 11111 FCVTZS (vector, fixed-point)
1 != 0000 00000 USHR
1 != 0000 00010 USRA
1 != 0000 00100 URSHR
1 != 0000 00110 URSRA
1 != 0000 01000 SRI
1 != 0000 01010 SLI
1 != 0000 01100 SQSHLU
1 != 0000 01110 UQSHL (immediate)
1 != 0000 10000 SQSHRUN, SQSHRUN2
1 != 0000 10001 SQRSHRUN, SQRSHRUN2
1 != 0000 10010 UQSHRN, UQSHRN2
1 != 0000 10011 UQRSHRN, UQRSHRN2
1 != 0000 11100 UCVTF (vector, fixed-point)
1 != 0000 11111 FCVTZU (vector, fixed-point)

Advanced SIMD scalar x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 U 1 1 1 1 1 size L M Rm opcode H 0 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
0000 UNALLOCATED -
0010 UNALLOCATED -
0100 UNALLOCATED -
0110 UNALLOCATED -
1000 UNALLOCATED -
1010 UNALLOCATED -
1110 UNALLOCATED -
01 0001 UNALLOCATED -
01 0101 UNALLOCATED -
01 1001 UNALLOCATED -
0 0011 SQDMLAL, SQDMLAL2 (by element) -
0 0111 SQDMLSL, SQDMLSL2 (by element) -
0 1011 SQDMULL, SQDMULL2 (by element) -
0 1100 SQDMULH (by element) -
0 1101 SQRDMULH (by element) -
0 1111 UNALLOCATED -
0 00 0001 FMLA (by element)half-precision Armv8.2
0 00 0101 FMLS (by element)half-precision Armv8.2
0 00 1001 FMUL (by element)half-precision Armv8.2
0 1x 0001 FMLA (by element)single-precision and double-precision -
0 1x 0101 FMLS (by element)single-precision and double-precision -
0 1x 1001 FMUL (by element)single-precision and double-precision -
1 0011 UNALLOCATED -
1 0111 UNALLOCATED -
1 1011 UNALLOCATED -
1 1100 UNALLOCATED -
1 1101 SQRDMLAH (by element) Armv8.1
1 1111 SQRDMLSH (by element) Armv8.1
1 00 0001 UNALLOCATED -
1 00 0101 UNALLOCATED -
1 00 1001 FMULX (by element)half-precision Armv8.2
1 1x 0001 UNALLOCATED -
1 1x 0101 UNALLOCATED -
1 1x 1001 FMULX (by element)single-precision and double-precision -

Advanced SIMD table lookup

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 1 0 op2 0 Rm 0 len op 0 0 Rn Rd
Decode fields Instruction Details
op2 len op
x1 UNALLOCATED
00 00 0 TBLsingle register table
00 00 1 TBXsingle register table
00 01 0 TBLtwo register table
00 01 1 TBXtwo register table
00 10 0 TBLthree register table
00 10 1 TBXthree register table
00 11 0 TBLfour register table
00 11 1 TBXfour register table
1x UNALLOCATED

Advanced SIMD permute

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 1 0 size 0 Rm 0 opcode 1 0 Rn Rd
Decode fields Instruction Details
opcode
000 UNALLOCATED
001 UZP1
010 TRN1
011 ZIP1
100 UNALLOCATED
101 UZP2
110 TRN2
111 ZIP2

Advanced SIMD extract

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 1 0 1 1 1 0 op2 0 Rm 0 imm4 0 Rn Rd
Decode fields Instruction Details
op2
x1 UNALLOCATED
00 EXT
1x UNALLOCATED

Advanced SIMD copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q op 0 1 1 1 0 0 0 0 imm5 0 imm4 1 Rn Rd
Decode fields Instruction Details
Q op imm5 imm4
x0000 UNALLOCATED
0 0000 DUP (element)
0 0001 DUP (general)
0 0010 UNALLOCATED
0 0100 UNALLOCATED
0 0110 UNALLOCATED
0 1xxx UNALLOCATED
0 0 0011 UNALLOCATED
0 0 0101 SMOV
0 0 0111 UMOV
0 1 UNALLOCATED
1 0 0011 INS (general)
1 0 0101 SMOV
1 0 x1000 0111 UMOV
1 1 INS (element)

Advanced SIMD three same (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 a 1 0 Rm 0 0 opcode 1 Rn Rd
Decode fields Instruction Details Architecture Version
U a opcode
0 0 000 FMAXNM (vector) Armv8.2
0 0 001 FMLA (vector) Armv8.2
0 0 010 FADD (vector) Armv8.2
0 0 011 FMULX Armv8.2
0 0 100 FCMEQ (register) Armv8.2
0 0 101 UNALLOCATED -
0 0 110 FMAX (vector) Armv8.2
0 0 111 FRECPS Armv8.2
0 1 000 FMINNM (vector) Armv8.2
0 1 001 FMLS (vector) Armv8.2
0 1 010 FSUB (vector) Armv8.2
0 1 011 UNALLOCATED -
0 1 100 UNALLOCATED -
0 1 101 UNALLOCATED -
0 1 110 FMIN (vector) Armv8.2
0 1 111 FRSQRTS Armv8.2
1 0 000 FMAXNMP (vector) Armv8.2
1 0 001 UNALLOCATED -
1 0 010 FADDP (vector) Armv8.2
1 0 011 FMUL (vector) Armv8.2
1 0 100 FCMGE (register) Armv8.2
1 0 101 FACGE Armv8.2
1 0 110 FMAXP (vector) Armv8.2
1 0 111 FDIV (vector) Armv8.2
1 1 000 FMINNMP (vector) Armv8.2
1 1 001 UNALLOCATED -
1 1 010 FABD Armv8.2
1 1 011 UNALLOCATED -
1 1 100 FCMGT (register) Armv8.2
1 1 101 FACGT Armv8.2
1 1 110 FMINP (vector) Armv8.2
1 1 111 UNALLOCATED -

Advanced SIMD two-register miscellaneous (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 a 1 1 1 1 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
U a opcode
00xxx UNALLOCATED -
010xx UNALLOCATED -
10xxx UNALLOCATED -
11110 UNALLOCATED -
0 011xx UNALLOCATED -
0 11111 UNALLOCATED -
1 11100 UNALLOCATED -
0 0 11000 FRINTN (vector) Armv8.2
0 0 11001 FRINTM (vector) Armv8.2
0 0 11010 FCVTNS (vector) Armv8.2
0 0 11011 FCVTMS (vector) Armv8.2
0 0 11100 FCVTAS (vector) Armv8.2
0 0 11101 SCVTF (vector, integer) Armv8.2
0 1 01100 FCMGT (zero) Armv8.2
0 1 01101 FCMEQ (zero) Armv8.2
0 1 01110 FCMLT (zero) Armv8.2
0 1 01111 FABS (vector) Armv8.2
0 1 11000 FRINTP (vector) Armv8.2
0 1 11001 FRINTZ (vector) Armv8.2
0 1 11010 FCVTPS (vector) Armv8.2
0 1 11011 FCVTZS (vector, integer) Armv8.2
0 1 11101 FRECPE Armv8.2
0 1 11111 UNALLOCATED -
1 0 11000 FRINTA (vector) Armv8.2
1 0 11001 FRINTX (vector) Armv8.2
1 0 11010 FCVTNU (vector) Armv8.2
1 0 11011 FCVTMU (vector) Armv8.2
1 0 11100 FCVTAU (vector) Armv8.2
1 0 11101 UCVTF (vector, integer) Armv8.2
1 1 01100 FCMGE (zero) Armv8.2
1 1 01101 FCMLE (zero) Armv8.2
1 1 01110 UNALLOCATED -
1 1 01111 FNEG (vector) Armv8.2
1 1 11000 UNALLOCATED -
1 1 11001 FRINTI (vector) Armv8.2
1 1 11010 FCVTPU (vector) Armv8.2
1 1 11011 FCVTZU (vector, integer) Armv8.2
1 1 11101 FRSQRTE Armv8.2
1 1 11111 FSQRT (vector) Armv8.2

Advanced SIMD three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 size 0 Rm 1 opcode 1 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
0011 UNALLOCATED -
01xx UNALLOCATED -
0 0000 UNALLOCATED -
0 0001 UNALLOCATED -
0 0010 SDOT (vector) Armv8.2
0 1xxx UNALLOCATED -
1 0000 SQRDMLAH (vector) Armv8.1
1 0001 SQRDMLSH (vector) Armv8.1
1 0010 UDOT (vector) Armv8.2
1 10xx FCMLA Armv8.3
1 11x0 FCADD Armv8.3
1 00 1101 UNALLOCATED -
1 00 1111 UNALLOCATED -
1 1x 1101 UNALLOCATED -
1 1x 1111 UNALLOCATED -

Advanced SIMD two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 size 1 0 0 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
1000x UNALLOCATED -
10101 UNALLOCATED -
0x 011xx UNALLOCATED -
1x 10111 UNALLOCATED -
1x 11110 UNALLOCATED -
11 10110 UNALLOCATED -
0 00000 REV64 -
0 00001 REV16 (vector) -
0 00010 SADDLP -
0 00011 SUQADD -
0 00100 CLS (vector) -
0 00101 CNT -
0 00110 SADALP -
0 00111 SQABS -
0 01000 CMGT (zero) -
0 01001 CMEQ (zero) -
0 01010 CMLT (zero) -
0 01011 ABS -
0 10010 XTN, XTN2 -
0 10011 UNALLOCATED -
0 10100 SQXTN, SQXTN2 -
0 0x 10110 FCVTN, FCVTN2 -
0 0x 10111 FCVTL, FCVTL2 -
0 0x 11000 FRINTN (vector) -
0 0x 11001 FRINTM (vector) -
0 0x 11010 FCVTNS (vector) -
0 0x 11011 FCVTMS (vector) -
0 0x 11100 FCVTAS (vector) -
0 0x 11101 SCVTF (vector, integer) -
0 0x 11110 FRINT32Z (vector) Armv8.5
0 0x 11111 FRINT64Z (vector) Armv8.5
0 1x 01100 FCMGT (zero) -
0 1x 01101 FCMEQ (zero) -
0 1x 01110 FCMLT (zero) -
0 1x 01111 FABS (vector) -
0 1x 11000 FRINTP (vector) -
0 1x 11001 FRINTZ (vector) -
0 1x 11010 FCVTPS (vector) -
0 1x 11011 FCVTZS (vector, integer) -
0 1x 11100 URECPE -
0 1x 11101 FRECPE -
0 1x 11111 UNALLOCATED -
1 00000 REV32 (vector) -
1 00001 UNALLOCATED -
1 00010 UADDLP -
1 00011 USQADD -
1 00100 CLZ (vector) -
1 00110 UADALP -
1 00111 SQNEG -
1 01000 CMGE (zero) -
1 01001 CMLE (zero) -
1 01010 UNALLOCATED -
1 01011 NEG (vector) -
1 10010 SQXTUN, SQXTUN2 -
1 10011 SHLL, SHLL2 -
1 10100 UQXTN, UQXTN2 -
1 0x 10110 FCVTXN, FCVTXN2 -
1 0x 10111 UNALLOCATED -
1 0x 11000 FRINTA (vector) -
1 0x 11001 FRINTX (vector) -
1 0x 11010 FCVTNU (vector) -
1 0x 11011 FCVTMU (vector) -
1 0x 11100 FCVTAU (vector) -
1 0x 11101 UCVTF (vector, integer) -
1 0x 11110 FRINT32X (vector) Armv8.5
1 0x 11111 FRINT64X (vector) Armv8.5
1 00 00101 NOT -
1 01 00101 RBIT (vector) -
1 1x 00101 UNALLOCATED -
1 1x 01100 FCMGE (zero) -
1 1x 01101 FCMLE (zero) -
1 1x 01110 UNALLOCATED -
1 1x 01111 FNEG (vector) -
1 1x 11000 UNALLOCATED -
1 1x 11001 FRINTI (vector) -
1 1x 11010 FCVTPU (vector) -
1 1x 11011 FCVTZU (vector, integer) -
1 1x 11100 URSQRTE -
1 1x 11101 FRSQRTE -
1 1x 11111 FSQRT (vector) -
1 10 10110 UNALLOCATED -

Advanced SIMD across lanes

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 size 1 1 0 0 0 opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
0000x UNALLOCATED -
00010 UNALLOCATED -
001xx UNALLOCATED -
0100x UNALLOCATED -
01011 UNALLOCATED -
01101 UNALLOCATED -
01110 UNALLOCATED -
10xxx UNALLOCATED -
1100x UNALLOCATED -
111xx UNALLOCATED -
0 00011 SADDLV -
0 01010 SMAXV -
0 11010 SMINV -
0 11011 ADDV -
0 00 01100 FMAXNMVhalf-precision Armv8.2
0 00 01111 FMAXVhalf-precision Armv8.2
0 01 01100 UNALLOCATED -
0 01 01111 UNALLOCATED -
0 10 01100 FMINNMVhalf-precision Armv8.2
0 10 01111 FMINVhalf-precision Armv8.2
0 11 01100 UNALLOCATED -
0 11 01111 UNALLOCATED -
1 00011 UADDLV -
1 01010 UMAXV -
1 11010 UMINV -
1 11011 UNALLOCATED -
1 0x 01100 FMAXNMVsingle-precision and double-precision -
1 0x 01111 FMAXVsingle-precision and double-precision -
1 1x 01100 FMINNMVsingle-precision and double-precision -
1 1x 01111 FMINVsingle-precision and double-precision -

Advanced SIMD three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 size 1 Rm opcode 0 0 Rn Rd
Decode fields Instruction Details
U opcode
1111 UNALLOCATED
0 0000 SADDL, SADDL2
0 0001 SADDW, SADDW2
0 0010 SSUBL, SSUBL2
0 0011 SSUBW, SSUBW2
0 0100 ADDHN, ADDHN2
0 0101 SABAL, SABAL2
0 0110 SUBHN, SUBHN2
0 0111 SABDL, SABDL2
0 1000 SMLAL, SMLAL2 (vector)
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1010 SMLSL, SMLSL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1100 SMULL, SMULL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
0 1110 PMULL, PMULL2
1 0000 UADDL, UADDL2
1 0001 UADDW, UADDW2
1 0010 USUBL, USUBL2
1 0011 USUBW, USUBW2
1 0100 RADDHN, RADDHN2
1 0101 UABAL, UABAL2
1 0110 RSUBHN, RSUBHN2
1 0111 UABDL, UABDL2
1 1000 UMLAL, UMLAL2 (vector)
1 1001 UNALLOCATED
1 1010 UMLSL, UMLSL2 (vector)
1 1011 UNALLOCATED
1 1100 UMULL, UMULL2 (vector)
1 1101 UNALLOCATED
1 1110 UNALLOCATED

Advanced SIMD three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 0 size 1 Rm opcode 1 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
0 00000 SHADD -
0 00001 SQADD -
0 00010 SRHADD -
0 00100 SHSUB -
0 00101 SQSUB -
0 00110 CMGT (register) -
0 00111 CMGE (register) -
0 01000 SSHL -
0 01001 SQSHL (register) -
0 01010 SRSHL -
0 01011 SQRSHL -
0 01100 SMAX -
0 01101 SMIN -
0 01110 SABD -
0 01111 SABA -
0 10000 ADD (vector) -
0 10001 CMTST -
0 10010 MLA (vector) -
0 10011 MUL (vector) -
0 10100 SMAXP -
0 10101 SMINP -
0 10110 SQDMULH (vector) -
0 10111 ADDP (vector) -
0 0x 11000 FMAXNM (vector) -
0 0x 11001 FMLA (vector) -
0 0x 11010 FADD (vector) -
0 0x 11011 FMULX -
0 0x 11100 FCMEQ (register) -
0 0x 11110 FMAX (vector) -
0 0x 11111 FRECPS -
0 00 00011 AND (vector) -
0 00 11101 FMLAL, FMLAL2 (vector)FMLAL Armv8.2
0 01 00011 BIC (vector, register) -
0 01 11101 UNALLOCATED -
0 1x 11000 FMINNM (vector) -
0 1x 11001 FMLS (vector) -
0 1x 11010 FSUB (vector) -
0 1x 11011 UNALLOCATED -
0 1x 11100 UNALLOCATED -
0 1x 11110 FMIN (vector) -
0 1x 11111 FRSQRTS -
0 10 00011 ORR (vector, register) -
0 10 11101 FMLSL, FMLSL2 (vector)FMLSL Armv8.2
0 11 00011 ORN (vector) -
0 11 11101 UNALLOCATED -
1 00000 UHADD -
1 00001 UQADD -
1 00010 URHADD -
1 00100 UHSUB -
1 00101 UQSUB -
1 00110 CMHI (register) -
1 00111 CMHS (register) -
1 01000 USHL -
1 01001 UQSHL (register) -
1 01010 URSHL -
1 01011 UQRSHL -
1 01100 UMAX -
1 01101 UMIN -
1 01110 UABD -
1 01111 UABA -
1 10000 SUB (vector) -
1 10001 CMEQ (register) -
1 10010 MLS (vector) -
1 10011 PMUL -
1 10100 UMAXP -
1 10101 UMINP -
1 10110 SQRDMULH (vector) -
1 10111 UNALLOCATED -
1 0x 11000 FMAXNMP (vector) -
1 0x 11010 FADDP (vector) -
1 0x 11011 FMUL (vector) -
1 0x 11100 FCMGE (register) -
1 0x 11101 FACGE -
1 0x 11110 FMAXP (vector) -
1 0x 11111 FDIV (vector) -
1 00 00011 EOR (vector) -
1 00 11001 FMLAL, FMLAL2 (vector)FMLAL2 Armv8.2
1 01 00011 BSL -
1 01 11001 UNALLOCATED -
1 1x 11000 FMINNMP (vector) -
1 1x 11010 FABD -
1 1x 11011 UNALLOCATED -
1 1x 11100 FCMGT (register) -
1 1x 11101 FACGT -
1 1x 11110 FMINP (vector) -
1 1x 11111 UNALLOCATED -
1 10 00011 BIT -
1 10 11001 FMLSL, FMLSL2 (vector)FMLSL2 Armv8.2
1 11 00011 BIF -
1 11 11001 UNALLOCATED -

Advanced SIMD modified immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q op 0 1 1 1 1 0 0 0 0 0 a b c cmode o2 1 d e f g h Rd
Decode fields Instruction Details Architecture Version
Q op cmode o2
0 0xxx 1 UNALLOCATED -
0 0xx0 0 MOVI32-bit shifted immediate -
0 0xx1 0 ORR (vector, immediate)32-bit -
0 10xx 1 UNALLOCATED -
0 10x0 0 MOVI16-bit shifted immediate -
0 10x1 0 ORR (vector, immediate)16-bit -
0 110x 0 MOVI32-bit shifting ones -
0 110x 1 UNALLOCATED -
0 1110 0 MOVI8-bit -
0 1110 1 UNALLOCATED -
0 1111 0 FMOV (vector, immediate)single-precision -
0 1111 1 FMOV (vector, immediate)half-precision Armv8.2
1 1 UNALLOCATED -
1 0xx0 0 MVNI32-bit shifted immediate -
1 0xx1 0 BIC (vector, immediate)32-bit -
1 10x0 0 MVNI16-bit shifted immediate -
1 10x1 0 BIC (vector, immediate)16-bit -
1 110x 0 MVNI32-bit shifting ones -
0 1 1110 0 MOVI64-bit scalar -
0 1 1111 0 UNALLOCATED -
1 1 1110 0 MOVI64-bit vector -
1 1 1111 0 FMOV (vector, immediate)double-precision -

Advanced SIMD shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 1 0 != 0000 immb opcode 1 Rn Rd
immh

The following constraints also apply to this encoding: immh != 0000 && immh != 0000

Decode fields Instruction Details
U opcode
00001 UNALLOCATED
00011 UNALLOCATED
00101 UNALLOCATED
00111 UNALLOCATED
01001 UNALLOCATED
01011 UNALLOCATED
01101 UNALLOCATED
01111 UNALLOCATED
10101 UNALLOCATED
1011x UNALLOCATED
110xx UNALLOCATED
11101 UNALLOCATED
11110 UNALLOCATED
0 00000 SSHR
0 00010 SSRA
0 00100 SRSHR
0 00110 SRSRA
0 01000 UNALLOCATED
0 01010 SHL
0 01100 UNALLOCATED
0 01110 SQSHL (immediate)
0 10000 SHRN, SHRN2
0 10001 RSHRN, RSHRN2
0 10010 SQSHRN, SQSHRN2
0 10011 SQRSHRN, SQRSHRN2
0 10100 SSHLL, SSHLL2
0 11100 SCVTF (vector, fixed-point)
0 11111 FCVTZS (vector, fixed-point)
1 00000 USHR
1 00010 USRA
1 00100 URSHR
1 00110 URSRA
1 01000 SRI
1 01010 SLI
1 01100 SQSHLU
1 01110 UQSHL (immediate)
1 10000 SQSHRUN, SQSHRUN2
1 10001 SQRSHRUN, SQRSHRUN2
1 10010 UQSHRN, UQSHRN2
1 10011 UQRSHRN, UQRSHRN2
1 10100 USHLL, USHLL2
1 11100 UCVTF (vector, fixed-point)
1 11111 FCVTZU (vector, fixed-point)

Advanced SIMD vector x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q U 0 1 1 1 1 size L M Rm opcode H 0 Rn Rd
Decode fields Instruction Details Architecture Version
U size opcode
01 1001 UNALLOCATED -
0 0010 SMLAL, SMLAL2 (by element) -
0 0011 SQDMLAL, SQDMLAL2 (by element) -
0 0110 SMLSL, SMLSL2 (by element) -
0 0111 SQDMLSL, SQDMLSL2 (by element) -
0 1000 MUL (by element) -
0 1010 SMULL, SMULL2 (by element) -
0 1011 SQDMULL, SQDMULL2 (by element) -
0 1100 SQDMULH (by element) -
0 1101 SQRDMULH (by element) -
0 1110 SDOT (by element) Armv8.2
0 0x 0000 UNALLOCATED -
0 0x 0100 UNALLOCATED -
0 00 0001 FMLA (by element)half-precision Armv8.2
0 00 0101 FMLS (by element)half-precision Armv8.2
0 00 1001 FMUL (by element)half-precision Armv8.2
0 00 1111 UNALLOCATED -
0 01 0001 UNALLOCATED -
0 01 0101 UNALLOCATED -
0 1x 0001 FMLA (by element)single-precision and double-precision -
0 1x 0101 FMLS (by element)single-precision and double-precision -
0 1x 1001 FMUL (by element)single-precision and double-precision -
0 1x 1111 UNALLOCATED -
0 10 0000 FMLAL, FMLAL2 (by element)FMLAL Armv8.2
0 10 0100 FMLSL, FMLSL2 (by element)FMLSL Armv8.2
0 11 0000 UNALLOCATED -
0 11 0100 UNALLOCATED -
1 0000 MLA (by element) -
1 0010 UMLAL, UMLAL2 (by element) -
1 0100 MLS (by element) -
1 0110 UMLSL, UMLSL2 (by element) -
1 1010 UMULL, UMULL2 (by element) -
1 1011 UNALLOCATED -
1 1101 SQRDMLAH (by element) Armv8.1
1 1110 UDOT (by element) Armv8.2
1 1111 SQRDMLSH (by element) Armv8.1
1 0x 1000 UNALLOCATED -
1 0x 1100 UNALLOCATED -
1 00 0001 UNALLOCATED -
1 00 0011 UNALLOCATED -
1 00 0101 UNALLOCATED -
1 00 0111 UNALLOCATED -
1 00 1001 FMULX (by element)half-precision Armv8.2
1 01 0xx1 FCMLA (by element) Armv8.3
1 1x 1001 FMULX (by element)single-precision and double-precision -
1 10 0xx1 FCMLA (by element) Armv8.3
1 10 1000 FMLAL, FMLAL2 (by element)FMLAL2 Armv8.2
1 10 1100 FMLSL, FMLSL2 (by element)FMLSL2 Armv8.2
1 11 0001 UNALLOCATED -
1 11 0011 UNALLOCATED -
1 11 0101 UNALLOCATED -
1 11 0111 UNALLOCATED -
1 11 1000 UNALLOCATED -
1 11 1100 UNALLOCATED -

Cryptographic three-register, imm2

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 1 0 Rm 1 0 imm2 opcode Rn Rd
Decode fields Instruction Details Architecture Version
opcode
00 SM3TT1A Armv8.2
01 SM3TT1B Armv8.2
10 SM3TT2A Armv8.2
11 SM3TT2B Armv8.2

Cryptographic three-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 1 1 Rm 1 O 0 0 opcode Rn Rd
Decode fields Instruction Details Architecture Version
O opcode
0 00 SHA512H Armv8.2
0 01 SHA512H2 Armv8.2
0 10 SHA512SU1 Armv8.2
0 11 RAX1 Armv8.2
1 00 SM3PARTW1 Armv8.2
1 01 SM3PARTW2 Armv8.2
1 10 SM4EKEY Armv8.2
1 11 UNALLOCATED -

Cryptographic four-register

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 Op0 Rm 0 Ra Rn Rd
Decode fields Instruction Details Architecture Version
Op0
00 EOR3 Armv8.2
01 BCAX Armv8.2
10 SM3SS1 Armv8.2
11 UNALLOCATED -

Cryptographic two-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 opcode Rn Rd
Decode fields Instruction Details Architecture Version
opcode
00 SHA512SU0 Armv8.2
01 SM4E Armv8.2
1x UNALLOCATED -

Conversion between floating-point and fixed-point

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf 0 S 1 1 1 1 0 type 0 rmode opcode scale Rn Rd
Decode fields Instruction Details Architecture Version
sf S type rmode opcode scale
1xx UNALLOCATED -
x0 00x UNALLOCATED -
x1 01x UNALLOCATED -
0x 00x UNALLOCATED -
1x 01x UNALLOCATED -
10 UNALLOCATED -
1 UNALLOCATED -
0 0xxxxx UNALLOCATED -
0 0 00 00 010 SCVTF (scalar, fixed-point)32-bit to single-precision -
0 0 00 00 011 UCVTF (scalar, fixed-point)32-bit to single-precision -
0 0 00 11 000 FCVTZS (scalar, fixed-point)single-precision to 32-bit -
0 0 00 11 001 FCVTZU (scalar, fixed-point)single-precision to 32-bit -
0 0 01 00 010 SCVTF (scalar, fixed-point)32-bit to double-precision -
0 0 01 00 011 UCVTF (scalar, fixed-point)32-bit to double-precision -
0 0 01 11 000 FCVTZS (scalar, fixed-point)double-precision to 32-bit -
0 0 01 11 001 FCVTZU (scalar, fixed-point)double-precision to 32-bit -
0 0 11 00 010 SCVTF (scalar, fixed-point)32-bit to half-precision Armv8.2
0 0 11 00 011 UCVTF (scalar, fixed-point)32-bit to half-precision Armv8.2
0 0 11 11 000 FCVTZS (scalar, fixed-point)half-precision to 32-bit Armv8.2
0 0 11 11 001 FCVTZU (scalar, fixed-point)half-precision to 32-bit Armv8.2
1 0 00 00 010 SCVTF (scalar, fixed-point)64-bit to single-precision -
1 0 00 00 011 UCVTF (scalar, fixed-point)64-bit to single-precision -
1 0 00 11 000 FCVTZS (scalar, fixed-point)single-precision to 64-bit -
1 0 00 11 001 FCVTZU (scalar, fixed-point)single-precision to 64-bit -
1 0 01 00 010 SCVTF (scalar, fixed-point)64-bit to double-precision -
1 0 01 00 011 UCVTF (scalar, fixed-point)64-bit to double-precision -
1 0 01 11 000 FCVTZS (scalar, fixed-point)double-precision to 64-bit -
1 0 01 11 001 FCVTZU (scalar, fixed-point)double-precision to 64-bit -
1 0 11 00 010 SCVTF (scalar, fixed-point)64-bit to half-precision Armv8.2
1 0 11 00 011 UCVTF (scalar, fixed-point)64-bit to half-precision Armv8.2
1 0 11 11 000 FCVTZS (scalar, fixed-point)half-precision to 64-bit Armv8.2
1 0 11 11 001 FCVTZU (scalar, fixed-point)half-precision to 64-bit Armv8.2

Conversion between floating-point and integer

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf 0 S 1 1 1 1 0 type 1 rmode opcode 0 0 0 0 0 0 Rn Rd
Decode fields Instruction Details Architecture Version
sf S type rmode opcode
x1 01x UNALLOCATED -
x1 10x UNALLOCATED -
1x 01x UNALLOCATED -
1x 10x UNALLOCATED -
0 10 0xx UNALLOCATED -
0 10 10x UNALLOCATED -
1 UNALLOCATED -
0 0 00 x1 11x UNALLOCATED -
0 0 00 00 000 FCVTNS (scalar)single-precision to 32-bit -
0 0 00 00 001 FCVTNU (scalar)single-precision to 32-bit -
0 0 00 00 010 SCVTF (scalar, integer)32-bit to single-precision -
0 0 00 00 011 UCVTF (scalar, integer)32-bit to single-precision -
0 0 00 00 100 FCVTAS (scalar)single-precision to 32-bit -
0 0 00 00 101 FCVTAU (scalar)single-precision to 32-bit -
0 0 00 00 110 FMOV (general)single-precision to 32-bit -
0 0 00 00 111 FMOV (general)32-bit to single-precision -
0 0 00 01 000 FCVTPS (scalar)single-precision to 32-bit -
0 0 00 01 001 FCVTPU (scalar)single-precision to 32-bit -
0 0 00 1x 11x UNALLOCATED -
0 0 00 10 000 FCVTMS (scalar)single-precision to 32-bit -
0 0 00 10 001 FCVTMU (scalar)single-precision to 32-bit -
0 0 00 11 000 FCVTZS (scalar, integer)single-precision to 32-bit -
0 0 00 11 001 FCVTZU (scalar, integer)single-precision to 32-bit -
0 0 01 0x 11x UNALLOCATED -
0 0 01 00 000 FCVTNS (scalar)double-precision to 32-bit -
0 0 01 00 001 FCVTNU (scalar)double-precision to 32-bit -
0 0 01 00 010 SCVTF (scalar, integer)32-bit to double-precision -
0 0 01 00 011 UCVTF (scalar, integer)32-bit to double-precision -
0 0 01 00 100 FCVTAS (scalar)double-precision to 32-bit -
0 0 01 00 101 FCVTAU (scalar)double-precision to 32-bit -
0 0 01 01 000 FCVTPS (scalar)double-precision to 32-bit -
0 0 01 01 001 FCVTPU (scalar)double-precision to 32-bit -
0 0 01 10 000 FCVTMS (scalar)double-precision to 32-bit -
0 0 01 10 001 FCVTMU (scalar)double-precision to 32-bit -
0 0 01 10 11x UNALLOCATED -
0 0 01 11 000 FCVTZS (scalar, integer)double-precision to 32-bit -
0 0 01 11 001 FCVTZU (scalar, integer)double-precision to 32-bit -
0 0 01 11 110 FJCVTZS Armv8.3
0 0 01 11 111 UNALLOCATED -
0 0 10 11x UNALLOCATED -
0 0 11 00 000 FCVTNS (scalar)half-precision to 32-bit Armv8.2
0 0 11 00 001 FCVTNU (scalar)half-precision to 32-bit Armv8.2
0 0 11 00 010 SCVTF (scalar, integer)32-bit to half-precision Armv8.2
0 0 11 00 011 UCVTF (scalar, integer)32-bit to half-precision Armv8.2
0 0 11 00 100 FCVTAS (scalar)half-precision to 32-bit Armv8.2
0 0 11 00 101 FCVTAU (scalar)half-precision to 32-bit Armv8.2
0 0 11 00 110 FMOV (general)half-precision to 32-bit Armv8.2
0 0 11 00 111 FMOV (general)32-bit to half-precision Armv8.2
0 0 11 01 000 FCVTPS (scalar)half-precision to 32-bit Armv8.2
0 0 11 01 001 FCVTPU (scalar)half-precision to 32-bit Armv8.2
0 0 11 10 000 FCVTMS (scalar)half-precision to 32-bit Armv8.2
0 0 11 10 001 FCVTMU (scalar)half-precision to 32-bit Armv8.2
0 0 11 11 000 FCVTZS (scalar, integer)half-precision to 32-bit Armv8.2
0 0 11 11 001 FCVTZU (scalar, integer)half-precision to 32-bit Armv8.2
1 0 00 11x UNALLOCATED -
1 0 00 00 000 FCVTNS (scalar)single-precision to 64-bit -
1 0 00 00 001 FCVTNU (scalar)single-precision to 64-bit -
1 0 00 00 010 SCVTF (scalar, integer)64-bit to single-precision -
1 0 00 00 011 UCVTF (scalar, integer)64-bit to single-precision -
1 0 00 00 100 FCVTAS (scalar)single-precision to 64-bit -
1 0 00 00 101 FCVTAU (scalar)single-precision to 64-bit -
1 0 00 01 000 FCVTPS (scalar)single-precision to 64-bit -
1 0 00 01 001 FCVTPU (scalar)single-precision to 64-bit -
1 0 00 10 000 FCVTMS (scalar)single-precision to 64-bit -
1 0 00 10 001 FCVTMU (scalar)single-precision to 64-bit -
1 0 00 11 000 FCVTZS (scalar, integer)single-precision to 64-bit -
1 0 00 11 001 FCVTZU (scalar, integer)single-precision to 64-bit -
1 0 01 x1 11x UNALLOCATED -
1 0 01 00 000 FCVTNS (scalar)double-precision to 64-bit -
1 0 01 00 001 FCVTNU (scalar)double-precision to 64-bit -
1 0 01 00 010 SCVTF (scalar, integer)64-bit to double-precision -
1 0 01 00 011 UCVTF (scalar, integer)64-bit to double-precision -
1 0 01 00 100 FCVTAS (scalar)double-precision to 64-bit -
1 0 01 00 101 FCVTAU (scalar)double-precision to 64-bit -
1 0 01 00 110 FMOV (general)double-precision to 64-bit -
1 0 01 00 111 FMOV (general)64-bit to double-precision -
1 0 01 01 000 FCVTPS (scalar)double-precision to 64-bit -
1 0 01 01 001 FCVTPU (scalar)double-precision to 64-bit -
1 0 01 1x 11x UNALLOCATED -
1 0 01 10 000 FCVTMS (scalar)double-precision to 64-bit -
1 0 01 10 001 FCVTMU (scalar)double-precision to 64-bit -
1 0 01 11 000 FCVTZS (scalar, integer)double-precision to 64-bit -
1 0 01 11 001 FCVTZU (scalar, integer)double-precision to 64-bit -
1 0 10 x0 11x UNALLOCATED -
1 0 10 01 110 FMOV (general)top half of 128-bit to 64-bit -
1 0 10 01 111 FMOV (general)64-bit to top half of 128-bit -
1 0 10 1x 11x UNALLOCATED -
1 0 11 00 000 FCVTNS (scalar)half-precision to 64-bit Armv8.2
1 0 11 00 001 FCVTNU (scalar)half-precision to 64-bit Armv8.2
1 0 11 00 010 SCVTF (scalar, integer)64-bit to half-precision Armv8.2
1 0 11 00 011 UCVTF (scalar, integer)64-bit to half-precision Armv8.2
1 0 11 00 100 FCVTAS (scalar)half-precision to 64-bit Armv8.2
1 0 11 00 101 FCVTAU (scalar)half-precision to 64-bit Armv8.2
1 0 11 00 110 FMOV (general)half-precision to 64-bit Armv8.2
1 0 11 00 111 FMOV (general)64-bit to half-precision Armv8.2
1 0 11 01 000 FCVTPS (scalar)half-precision to 64-bit Armv8.2
1 0 11 01 001 FCVTPU (scalar)half-precision to 64-bit Armv8.2
1 0 11 10 000 FCVTMS (scalar)half-precision to 64-bit Armv8.2
1 0 11 10 001 FCVTMU (scalar)half-precision to 64-bit Armv8.2
1 0 11 11 000 FCVTZS (scalar, integer)half-precision to 64-bit Armv8.2
1 0 11 11 001 FCVTZU (scalar, integer)half-precision to 64-bit Armv8.2

Floating-point data-processing (1 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 opcode 1 0 0 0 0 Rn Rd
Decode fields Instruction Details Architecture Version
M S type opcode
1xxxxx UNALLOCATED -
1 UNALLOCATED -
0 0 00 000000 FMOV (register)single-precision -
0 0 00 000001 FABS (scalar)single-precision -
0 0 00 000010 FNEG (scalar)single-precision -
0 0 00 000011 FSQRT (scalar)single-precision -
0 0 00 000100 UNALLOCATED -
0 0 00 000101 FCVTsingle-precision to double-precision -
0 0 00 000110 UNALLOCATED -
0 0 00 000111 FCVTsingle-precision to half-precision -
0 0 00 001000 FRINTN (scalar)single-precision -
0 0 00 001001 FRINTP (scalar)single-precision -
0 0 00 001010 FRINTM (scalar)single-precision -
0 0 00 001011 FRINTZ (scalar)single-precision -
0 0 00 001100 FRINTA (scalar)single-precision -
0 0 00 001101 UNALLOCATED -
0 0 00 001110 FRINTX (scalar)single-precision -
0 0 00 001111 FRINTI (scalar)single-precision -
0 0 00 010000 FRINT32Z (scalar)single-precision Armv8.5
0 0 00 010001 FRINT32X (scalar)single-precision Armv8.5
0 0 00 010010 FRINT64Z (scalar)single-precision Armv8.5
0 0 00 010011 FRINT64X (scalar)single-precision Armv8.5
0 0 00 0101xx UNALLOCATED -
0 0 00 011xxx UNALLOCATED -
0 0 01 000000 FMOV (register)double-precision -
0 0 01 000001 FABS (scalar)double-precision -
0 0 01 000010 FNEG (scalar)double-precision -
0 0 01 000011 FSQRT (scalar)double-precision -
0 0 01 000100 FCVTdouble-precision to single-precision -
0 0 01 000101 UNALLOCATED -
0 0 01 000111 FCVTdouble-precision to half-precision -
0 0 01 001000 FRINTN (scalar)double-precision -
0 0 01 001001 FRINTP (scalar)double-precision -
0 0 01 001010 FRINTM (scalar)double-precision -
0 0 01 001011 FRINTZ (scalar)double-precision -
0 0 01 001100 FRINTA (scalar)double-precision -
0 0 01 001101 UNALLOCATED -
0 0 01 001110 FRINTX (scalar)double-precision -
0 0 01 001111 FRINTI (scalar)double-precision -
0 0 01 010000 FRINT32Z (scalar)double-precision Armv8.5
0 0 01 010001 FRINT32X (scalar)double-precision Armv8.5
0 0 01 010010 FRINT64Z (scalar)double-precision Armv8.5
0 0 01 010011 FRINT64X (scalar)double-precision Armv8.5
0 0 01 0101xx UNALLOCATED -
0 0 01 011xxx UNALLOCATED -
0 0 10 0xxxxx UNALLOCATED -
0 0 11 000000 FMOV (register)half-precision Armv8.2
0 0 11 000001 FABS (scalar)half-precision Armv8.2
0 0 11 000010 FNEG (scalar)half-precision Armv8.2
0 0 11 000011 FSQRT (scalar)half-precision Armv8.2
0 0 11 000100 FCVThalf-precision to single-precision -
0 0 11 000101 FCVThalf-precision to double-precision -
0 0 11 00011x UNALLOCATED -
0 0 11 001000 FRINTN (scalar)half-precision Armv8.2
0 0 11 001001 FRINTP (scalar)half-precision Armv8.2
0 0 11 001010 FRINTM (scalar)half-precision Armv8.2
0 0 11 001011 FRINTZ (scalar)half-precision Armv8.2
0 0 11 001100 FRINTA (scalar)half-precision Armv8.2
0 0 11 001101 UNALLOCATED -
0 0 11 001110 FRINTX (scalar)half-precision Armv8.2
0 0 11 001111 FRINTI (scalar)half-precision Armv8.2
0 0 11 01xxxx UNALLOCATED -
1 UNALLOCATED -

Floating-point compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 Rm op 1 0 0 0 Rn opcode2
Decode fields Instruction Details Architecture Version
M S type op opcode2
xxxx1 UNALLOCATED -
xxx1x UNALLOCATED -
xx1xx UNALLOCATED -
x1 UNALLOCATED -
1x UNALLOCATED -
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 00 00000 FCMP -
0 0 00 00 01000 FCMP -
0 0 00 00 10000 FCMPE -
0 0 00 00 11000 FCMPE -
0 0 01 00 00000 FCMP -
0 0 01 00 01000 FCMP -
0 0 01 00 10000 FCMPE -
0 0 01 00 11000 FCMPE -
0 0 11 00 00000 FCMP Armv8.2
0 0 11 00 01000 FCMP Armv8.2
0 0 11 00 10000 FCMPE Armv8.2
0 0 11 00 11000 FCMPE Armv8.2
1 UNALLOCATED -

Floating-point immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 imm8 1 0 0 imm5 Rd
Decode fields Instruction Details Architecture Version
M S type imm5
xxxx1 UNALLOCATED -
xxx1x UNALLOCATED -
xx1xx UNALLOCATED -
x1xxx UNALLOCATED -
1xxxx UNALLOCATED -
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 00000 FMOV (scalar, immediate)single-precision -
0 0 01 00000 FMOV (scalar, immediate)double-precision -
0 0 11 00000 FMOV (scalar, immediate)half-precision Armv8.2
1 UNALLOCATED -

Floating-point conditional compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 Rm cond 0 1 Rn op nzcv
Decode fields Instruction Details Architecture Version
M S type op
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 0 FCCMPsingle-precision -
0 0 00 1 FCCMPEsingle-precision -
0 0 01 0 FCCMPdouble-precision -
0 0 01 1 FCCMPEdouble-precision -
0 0 11 0 FCCMPhalf-precision Armv8.2
0 0 11 1 FCCMPEhalf-precision Armv8.2
1 UNALLOCATED -

Floating-point data-processing (2 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 Rm opcode 1 0 Rn Rd
Decode fields Instruction Details Architecture Version
M S type opcode
1xx1 UNALLOCATED -
1x1x UNALLOCATED -
11xx UNALLOCATED -
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 0000 FMUL (scalar)single-precision -
0 0 00 0001 FDIV (scalar)single-precision -
0 0 00 0010 FADD (scalar)single-precision -
0 0 00 0011 FSUB (scalar)single-precision -
0 0 00 0100 FMAX (scalar)single-precision -
0 0 00 0101 FMIN (scalar)single-precision -
0 0 00 0110 FMAXNM (scalar)single-precision -
0 0 00 0111 FMINNM (scalar)single-precision -
0 0 00 1000 FNMUL (scalar)single-precision -
0 0 01 0000 FMUL (scalar)double-precision -
0 0 01 0001 FDIV (scalar)double-precision -
0 0 01 0010 FADD (scalar)double-precision -
0 0 01 0011 FSUB (scalar)double-precision -
0 0 01 0100 FMAX (scalar)double-precision -
0 0 01 0101 FMIN (scalar)double-precision -
0 0 01 0110 FMAXNM (scalar)double-precision -
0 0 01 0111 FMINNM (scalar)double-precision -
0 0 01 1000 FNMUL (scalar)double-precision -
0 0 11 0000 FMUL (scalar)half-precision Armv8.2
0 0 11 0001 FDIV (scalar)half-precision Armv8.2
0 0 11 0010 FADD (scalar)half-precision Armv8.2
0 0 11 0011 FSUB (scalar)half-precision Armv8.2
0 0 11 0100 FMAX (scalar)half-precision Armv8.2
0 0 11 0101 FMIN (scalar)half-precision Armv8.2
0 0 11 0110 FMAXNM (scalar)half-precision Armv8.2
0 0 11 0111 FMINNM (scalar)half-precision Armv8.2
0 0 11 1000 FNMUL (scalar)half-precision Armv8.2
1 UNALLOCATED -

Floating-point conditional select

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 0 type 1 Rm cond 1 1 Rn Rd
Decode fields Instruction Details Architecture Version
M S type
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 FCSELsingle-precision -
0 0 01 FCSELdouble-precision -
0 0 11 FCSELhalf-precision Armv8.2
1 UNALLOCATED -

Floating-point data-processing (3 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M 0 S 1 1 1 1 1 type o1 Rm o0 Ra Rn Rd
Decode fields Instruction Details Architecture Version
M S type o1 o0
10 UNALLOCATED -
1 UNALLOCATED -
0 0 00 0 0 FMADDsingle-precision -
0 0 00 0 1 FMSUBsingle-precision -
0 0 00 1 0 FNMADDsingle-precision -
0 0 00 1 1 FNMSUBsingle-precision -
0 0 01 0 0 FMADDdouble-precision -
0 0 01 0 1 FMSUBdouble-precision -
0 0 01 1 0 FNMADDdouble-precision -
0 0 01 1 1 FNMSUBdouble-precision -
0 0 11 0 0 FMADDhalf-precision Armv8.2
0 0 11 0 1 FMSUBhalf-precision Armv8.2
0 0 11 1 0 FNMADDhalf-precision Armv8.2
0 0 11 1 1 FNMSUBhalf-precision Armv8.2
1 UNALLOCATED -
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