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FADDA
Floating-point add strictly-ordered reduction, accumulating in scalar.
Floating-point add a SIMD&FP scalar source and all active lanes of the vector source and place the result destructively in the SIMD&FP scalar source register. Vector elements are processed strictly in order from low to high, with the scalar source providing the initial value. Inactive elements in the source vector are ignored.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | Zm | Vdn |
if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Vdn); integer m = UInt(Zm);
Assembler Symbols
<V> |
Is a width specifier,
encoded in
size:
|
<dn> |
Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
<T> |
Is the size specifier,
encoded in
size:
|
Operation
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(esize) operand1 = V[dn]; bits(VL) operand2 = Z[m]; bits(esize) result = operand1; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(esize) element = Elem[operand2, e, esize]; result = FPAdd(result, element, FPCR); V[dn] = result;