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## UZP1, UZP2 (vectors)

Concatenate even or odd elements from two vectors.

Concatenate adjacent even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated.

It has encodings from 2 classes: Even and Odd

### Even

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 size 1 Zm 0 1 1 0 1 0 Zn Zd

#### Even

UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

```if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 0;```

### Odd

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 size 1 Zm 0 1 1 0 1 1 Zn Zd

#### Odd

UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

```if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 1;```

### Assembler Symbols

 Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
 Is the name of the first source scalable vector register, encoded in the "Zn" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

### Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) result;

bits(VL*2) zipped = operand2:operand1;
for e = 0 to elements-1
Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];

Z[d] = result;```