CAS, CASA, CASAL, CASL
Compare and Swap word or doubleword in memory reads a 32-bit word or 64-bit doubleword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.
- CASA and CASAL load from memory with acquire semantics.
- CASL and CASAL store to memory with release semantics.
- CAS has no memory ordering requirements.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.
If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, or <Xs>, is restored to the value held in the register before the instruction was executed.
if !HaveAtomicExt() then UNDEFINED; integer n = UInt(Rn); integer t = UInt(Rt); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if L == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if o0 == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; boolean tag_checked = n != 31;
Is the 32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
Is the 32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.
Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
bits(64) address; bits(datasize) comparevalue; bits(datasize) newvalue; bits(datasize) data; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); comparevalue = X[s]; newvalue = X[t]; if n == 31 then CheckSPAlignment(); address = SP; else address = X[n]; data = MemAtomicCompareAndSwap(address, comparevalue, newvalue, ldacctype, stacctype); X[s] = ZeroExtend(data, regsize);