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Top-level encodings for A64

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0

Reserved

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 0000 op1
Decode fields Instruction details
op0 op1
000 000000000 UDF
!= 000000000 UNALLOCATED
!= 000 UNALLOCATED

SVE encodings

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 0010 op1 op2 op3
Decode fields Instruction details
op0 op1 op2 op3
000 0x 0xxxx x1xxxx SVE Integer Multiply-Add - Predicated
000 0x 0xxxx 000xxx SVE Integer Binary Arithmetic - Predicated
000 0x 0xxxx 001xxx SVE Integer Reduction
000 0x 0xxxx 100xxx SVE Bitwise Shift - Predicated
000 0x 0xxxx 101xxx SVE Integer Unary Arithmetic - Predicated
000 0x 1xxxx 000xxx SVE integer add/subtract vectors (unpredicated)
000 0x 1xxxx 001xxx SVE Bitwise Logical - Unpredicated
000 0x 1xxxx 0100xx SVE Index Generation
000 0x 1xxxx 0101xx SVE Stack Allocation
000 0x 1xxxx 011xxx UNALLOCATED
000 0x 1xxxx 100xxx SVE Bitwise Shift - Unpredicated
000 0x 1xxxx 1010xx SVE address generation
000 0x 1xxxx 1011xx SVE Integer Misc - Unpredicated
000 0x 1xxxx 11xxxx SVE Element Count
000 1x 00xxx SVE Bitwise Immediate
000 1x 01xxx SVE Integer Wide Immediate - Predicated
000 1x 1xxxx 001xxx SVE Permute Vector - Unpredicated
000 1x 1xxxx 010xxx SVE Permute Predicate
000 1x 1xxxx 011xxx SVE permute vector elements
000 1x 1xxxx 10xxxx SVE Permute Vector - Predicated
000 1x 1xxxx 11xxxx SEL (vectors)
000 10 1xxxx 000xxx SVE Permute Vector - Extract
000 11 1xxxx 000xxx UNALLOCATED
001 0x 0xxxx SVE Integer Compare - Vectors
001 0x 1xxxx SVE integer compare with unsigned immediate
001 1x 0xxxx x0xxxx SVE integer compare with signed immediate
001 1x 00xxx 01xxxx SVE predicate logical operations
001 1x 00xxx 11xxxx SVE Propagate Break
001 1x 01xxx 01xxxx SVE Partition Break
001 1x 01xxx 11xxxx SVE Predicate Misc
001 1x 1xxxx 00xxxx SVE Integer Compare - Scalars
001 1x 1xxxx 01xxxx UNALLOCATED
001 1x 1xxxx 11xxxx SVE Integer Wide Immediate - Unpredicated
001 1x 100xx 10xxxx SVE predicate count
001 1x 101xx 1000xx SVE Inc/Dec by Predicate Count
001 1x 101xx 1001xx SVE Write FFR
001 1x 101xx 101xxx UNALLOCATED
001 1x 11xxx 10xxxx UNALLOCATED
010 0x 0xxxx 0xxxxx SVE Integer Multiply-Add - Unpredicated
010 0x 0xxxx 1xxxxx UNALLOCATED
010 0x 1xxxx SVE Multiply - Indexed
010 1x UNALLOCATED
011 0x 0xxxx 0xxxxx FCMLA (vectors)
011 0x 00000 100xxx FCADD
011 0x 00000 101xxx UNALLOCATED
011 0x 00000 11xxxx UNALLOCATED
011 0x 00001 1xxxxx UNALLOCATED
011 0x 0001x 1xxxxx UNALLOCATED
011 0x 001xx 1xxxxx UNALLOCATED
011 0x 01xxx 1xxxxx UNALLOCATED
011 0x 1xxxx 00x01x UNALLOCATED
011 0x 1xxxx 00000x SVE floating-point multiply-add (indexed)
011 0x 1xxxx 0001xx SVE floating-point complex multiply-add (indexed)
011 0x 1xxxx 001000 SVE floating-point multiply (indexed)
011 0x 1xxxx 001001 UNALLOCATED
011 0x 1xxxx 0011xx UNALLOCATED
011 0x 1xxxx 01xxxx UNALLOCATED
011 0x 1xxxx 1xxxxx UNALLOCATED
011 1x 0xxxx x1xxxx SVE floating-point compare vectors
011 1x 0xxxx 000xxx SVE floating-point arithmetic (unpredicated)
011 1x 0xxxx 100xxx SVE Floating Point Arithmetic - Predicated
011 1x 0xxxx 101xxx SVE Floating Point Unary Operations - Predicated
011 1x 000xx 001xxx SVE floating-point recursive reduction
011 1x 001xx 0010xx UNALLOCATED
011 1x 001xx 0011xx SVE Floating Point Unary Operations - Unpredicated
011 1x 010xx 001xxx SVE Floating Point Compare - with Zero
011 1x 011xx 001xxx SVE floating-point serial reduction (predicated)
011 1x 1xxxx SVE Floating Point Multiply-Add
100 SVE Memory - 32-bit Gather and Unsized Contiguous
101 SVE Memory - Contiguous Load
110 SVE Memory - 64-bit Gather
111 SVE Memory - Store

SVE Integer Multiply-Add - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 0 op0 1

SVE integer multiply-accumulate writing addend (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 Zm 0 1 op Pg Zn Zda
Decode fields Instruction Details
op
0 MLA
1 MLS

SVE integer multiply-add writing multiplicand (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 Zm 1 1 op Pg Za Zdn
Decode fields Instruction Details
op
0 MAD
1 MSB

SVE Integer Binary Arithmetic - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 0 op0 000

SVE integer add/subtract vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 0 0 opc 0 0 0 Pg Zm Zdn
Decode fields Instruction Details
opc
000 ADD (vectors, predicated)
001 SUB (vectors, predicated)
010 UNALLOCATED
011 SUBR (vectors)
1xx UNALLOCATED

SVE integer min/max/difference (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 0 1 opc U 0 0 0 Pg Zm Zdn
Decode fields Instruction Details
opc U
00 0 SMAX (vectors)
00 1 UMAX (vectors)
01 0 SMIN (vectors)
01 1 UMIN (vectors)
10 0 SABD
10 1 UABD
11 UNALLOCATED

SVE integer multiply vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 0 0 H U 0 0 0 Pg Zm Zdn
Decode fields Instruction Details
H U
0 0 MUL (vectors)
0 1 UNALLOCATED
1 0 SMULH
1 1 UMULH

SVE integer divide vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 0 1 R U 0 0 0 Pg Zm Zdn
Decode fields Instruction Details
R U
0 0 SDIV
0 1 UDIV
1 0 SDIVR
1 1 UDIVR

SVE bitwise logical operations (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 1 opc 0 0 0 Pg Zm Zdn
Decode fields Instruction Details
opc
000 ORR (vectors, predicated)
001 EOR (vectors, predicated)
010 AND (vectors, predicated)
011 BIC (vectors, predicated)
1xx UNALLOCATED

SVE Integer Reduction

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 0 op0 001

SVE integer add reduction (predicated)

These instructions are under SVE Integer Reduction.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 0 0 opc U 0 0 1 Pg Zn Vd
Decode fields Instruction Details
opc U
00 0 SADDV
00 1 UADDV
01 UNALLOCATED
1x UNALLOCATED

SVE integer min/max reduction (predicated)

These instructions are under SVE Integer Reduction.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 0 1 opc U 0 0 1 Pg Zn Vd
Decode fields Instruction Details
opc U
00 0 SMAXV
00 1 UMAXV
01 0 SMINV
01 1 UMINV
1x UNALLOCATED

SVE constructive prefix (predicated)

These instructions are under SVE Integer Reduction.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 0 opc M 0 0 1 Pg Zn Zd
Decode fields Instruction Details
opc
00 MOVPRFX (predicated)
01 UNALLOCATED
1x UNALLOCATED

SVE bitwise logical reduction (predicated)

These instructions are under SVE Integer Reduction.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 1 opc 0 0 1 Pg Zn Vd
Decode fields Instruction Details
opc
000 ORV
001 EORV
010 ANDV
011 UNALLOCATED
1xx UNALLOCATED

SVE Bitwise Shift - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 0 op0 100

SVE bitwise shift by immediate (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 tszh 0 0 opc L U 1 0 0 Pg tszl imm3 Zdn
Decode fields Instruction Details
opc L U
00 0 0 ASR (immediate, predicated)
00 0 1 LSR (immediate, predicated)
00 1 0 UNALLOCATED
00 1 1 LSL (immediate, predicated)
01 0 0 ASRD
01 0 1 UNALLOCATED
01 1 UNALLOCATED
1x UNALLOCATED

SVE bitwise shift by vector (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 0 R L U 1 0 0 Pg Zm Zdn
Decode fields Instruction Details
R L U
1 0 UNALLOCATED
0 0 0 ASR (vectors)
0 0 1 LSR (vectors)
0 1 1 LSL (vectors)
1 0 0 ASRR
1 0 1 LSRR
1 1 1 LSLR

SVE bitwise shift by wide elements (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 1 R L U 1 0 0 Pg Zm Zdn
Decode fields Instruction Details
R L U
0 0 0 ASR (wide elements, predicated)
0 0 1 LSR (wide elements, predicated)
0 1 0 UNALLOCATED
0 1 1 LSL (wide elements, predicated)
1 UNALLOCATED

SVE Integer Unary Arithmetic - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 0 op0 101
Decode fields Instruction details
op0
0x UNALLOCATED
10 SVE integer unary operations (predicated)
11 SVE bitwise unary operations (predicated)

SVE integer unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 0 opc 1 0 1 Pg Zn Zd
Decode fields Instruction Details
opc
000 SXTB, SXTH, SXTWSXTB
001 UXTB, UXTH, UXTWUXTB
010 SXTB, SXTH, SXTWSXTH
011 UXTB, UXTH, UXTWUXTH
100 SXTB, SXTH, SXTWSXTW
101 UXTB, UXTH, UXTWUXTW
110 ABS
111 NEG

SVE bitwise unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 0 1 1 opc 1 0 1 Pg Zn Zd
Decode fields Instruction Details
opc
000 CLS
001 CLZ
010 CNT
011 CNOT
100 FABS
101 FNEG
110 NOT (vector)
111 UNALLOCATED

SVE integer add/subtract vectors (unpredicated)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 Zm 0 0 0 opc Zn Zd
Decode fields Instruction Details
opc
000 ADD (vectors, unpredicated)
001 SUB (vectors, unpredicated)
01x UNALLOCATED
100 SQADD (vectors)
101 UQADD (vectors)
110 SQSUB (vectors)
111 UQSUB (vectors)

SVE Bitwise Logical - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 1 001 op0 op1
Decode fields Instruction details
op0 op1
0 UNALLOCATED
1 00 SVE bitwise logical operations (unpredicated)
1 != 00 UNALLOCATED

SVE bitwise logical operations (unpredicated)

These instructions are under SVE Bitwise Logical - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 opc 1 Zm 0 0 1 1 0 0 Zn Zd

SVE Index Generation

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 1 0100 op0

SVE Stack Allocation

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 op0 1 0101 op1
Decode fields Instruction details
op0 op1
0 0 SVE stack frame adjustment
1 0 SVE stack frame size
1 UNALLOCATED

SVE stack frame adjustment

These instructions are under SVE Stack Allocation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 op 1 Rn 0 1 0 1 0 imm6 Rd
Decode fields Instruction Details
op
0 ADDVL
1 ADDPL

SVE stack frame size

These instructions are under SVE Stack Allocation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 1 op 1 opc2 0 1 0 1 0 imm6 Rd
Decode fields Instruction Details
op opc2
0 0xxxx UNALLOCATED
0 10xxx UNALLOCATED
0 110xx UNALLOCATED
0 1110x UNALLOCATED
0 11110 UNALLOCATED
0 11111 RDVL
1 UNALLOCATED

SVE Bitwise Shift - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 1 100 op0

SVE bitwise shift by wide elements (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 Zm 1 0 0 0 opc Zn Zd
Decode fields Instruction Details
opc
00 ASR (wide elements, unpredicated)
01 LSR (wide elements, unpredicated)
10 UNALLOCATED
11 LSL (wide elements, unpredicated)

SVE bitwise shift by immediate (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 tszh 1 tszl imm3 1 0 0 1 opc Zn Zd
Decode fields Instruction Details
opc
00 ASR (immediate, unpredicated)
01 LSR (immediate, unpredicated)
10 UNALLOCATED
11 LSL (immediate, unpredicated)

SVE address generation

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 opc 1 Zm 1 0 1 0 msz Zn Zd
Decode fields Instruction Details
opc
00 ADRUnpacked 32-bit signed offsets
01 ADRUnpacked 32-bit unsigned offsets
1x ADRPacked offsets

SVE Integer Misc - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 1 1011 op0

SVE floating-point trig select coefficient

These instructions are under SVE Integer Misc - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 Zm 1 0 1 1 0 op Zn Zd
Decode fields Instruction Details
op
0 FTSSEL
1 UNALLOCATED

SVE floating-point exponential accelerator

These instructions are under SVE Integer Misc - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 opc 1 0 1 1 1 0 Zn Zd
Decode fields Instruction Details
opc
00000 FEXPA
00001 UNALLOCATED
0001x UNALLOCATED
001xx UNALLOCATED
01xxx UNALLOCATED
1xxxx UNALLOCATED

SVE constructive prefix (unpredicated)

These instructions are under SVE Integer Misc - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 opc 1 opc2 1 0 1 1 1 1 Zn Zd
Decode fields Instruction Details
opc opc2
00 00000 MOVPRFX (unpredicated)
00 00001 UNALLOCATED
00 0001x UNALLOCATED
00 001xx UNALLOCATED
00 01xxx UNALLOCATED
00 1xxxx UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE Element Count

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000100 1 op0 11 op1
Decode fields Instruction details
op0 op1
0 00x SVE saturating inc/dec vector by element count
0 100 SVE element count
0 101 UNALLOCATED
1 000 SVE inc/dec vector by element count
1 100 SVE inc/dec register by element count
1 x01 UNALLOCATED
01x UNALLOCATED
11x SVE saturating inc/dec register by element count

SVE saturating inc/dec vector by element count

These instructions are under SVE Element Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 0 imm4 1 1 0 0 D U pattern Zdn
Decode fields Instruction Details
size D U
00 UNALLOCATED
01 0 0 SQINCH (vector)
01 0 1 UQINCH (vector)
01 1 0 SQDECH (vector)
01 1 1 UQDECH (vector)
10 0 0 SQINCW (vector)
10 0 1 UQINCW (vector)
10 1 0 SQDECW (vector)
10 1 1 UQDECW (vector)
11 0 0 SQINCD (vector)
11 0 1 UQINCD (vector)
11 1 0 SQDECD (vector)
11 1 1 UQDECD (vector)

SVE element count

These instructions are under SVE Element Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 0 imm4 1 1 1 0 0 op pattern Rd
Decode fields Instruction Details
size op
1 UNALLOCATED
00 0 CNTB, CNTD, CNTH, CNTWCNTB
01 0 CNTB, CNTD, CNTH, CNTWCNTH
10 0 CNTB, CNTD, CNTH, CNTWCNTW
11 0 CNTB, CNTD, CNTH, CNTWCNTD

SVE inc/dec vector by element count

These instructions are under SVE Element Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 1 imm4 1 1 0 0 0 D pattern Zdn
Decode fields Instruction Details
size D
00 UNALLOCATED
01 0 INCD, INCH, INCW (vector)INCH
01 1 DECD, DECH, DECW (vector)DECH
10 0 INCD, INCH, INCW (vector)INCW
10 1 DECD, DECH, DECW (vector)DECW
11 0 INCD, INCH, INCW (vector)INCD
11 1 DECD, DECH, DECW (vector)DECD

SVE inc/dec register by element count

These instructions are under SVE Element Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 1 imm4 1 1 1 0 0 D pattern Rdn

SVE saturating inc/dec register by element count

These instructions are under SVE Element Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 size 1 sf imm4 1 1 1 1 D U pattern Rdn
Decode fields Instruction Details
size sf D U
00 0 0 0 SQINCB32-bit
00 0 0 1 UQINCB32-bit
00 0 1 0 SQDECB32-bit
00 0 1 1 UQDECB32-bit
00 1 0 0 SQINCB64-bit
00 1 0 1 UQINCB64-bit
00 1 1 0 SQDECB64-bit
00 1 1 1 UQDECB64-bit
01 0 0 0 SQINCH (scalar)32-bit
01 0 0 1 UQINCH (scalar)32-bit
01 0 1 0 SQDECH (scalar)32-bit
01 0 1 1 UQDECH (scalar)32-bit
01 1 0 0 SQINCH (scalar)64-bit
01 1 0 1 UQINCH (scalar)64-bit
01 1 1 0 SQDECH (scalar)64-bit
01 1 1 1 UQDECH (scalar)64-bit
10 0 0 0 SQINCW (scalar)32-bit
10 0 0 1 UQINCW (scalar)32-bit
10 0 1 0 SQDECW (scalar)32-bit
10 0 1 1 UQDECW (scalar)32-bit
10 1 0 0 SQINCW (scalar)64-bit
10 1 0 1 UQINCW (scalar)64-bit
10 1 1 0 SQDECW (scalar)64-bit
10 1 1 1 UQDECW (scalar)64-bit
11 0 0 0 SQINCD (scalar)32-bit
11 0 0 1 UQINCD (scalar)32-bit
11 0 1 0 SQDECD (scalar)32-bit
11 0 1 1 UQDECD (scalar)32-bit
11 1 0 0 SQINCD (scalar)64-bit
11 1 0 1 UQINCD (scalar)64-bit
11 1 1 0 SQDECD (scalar)64-bit
11 1 1 1 UQDECD (scalar)64-bit

SVE Bitwise Immediate

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000101 00 op0
Decode fields Instruction details
op0
00 SVE bitwise logical with immediate (unpredicated)
!= 00 UNALLOCATED

SVE bitwise logical with immediate (unpredicated)

These instructions are under SVE Bitwise Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 opc 0 0 0 0 imm13 Zdn
Decode fields Instruction Details
opc
00 ORR (immediate)
01 EOR (immediate)
10 AND (immediate)

SVE Integer Wide Immediate - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000101 01 op0
Decode fields Instruction details
op0
0xx CPY (immediate)
10x UNALLOCATED
110 FCPY
111 UNALLOCATED

SVE Permute Vector - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000101 1 op0 op1 001 op2 op3
Decode fields Instruction details
op0 op1 op2 op3
000 00 1 10 DUP (scalar)
001 00 1 10 INSR (scalar)
00x 00 0 != 00 UNALLOCATED
00x 00 1 x1 UNALLOCATED
00x != 00 01 UNALLOCATED
00x != 00 1x UNALLOCATED
01x != 00 UNALLOCATED
100 0 != 00 UNALLOCATED
100 1 10 SVE unpack vector elements
100 1 x1 UNALLOCATED
101 00 0 != 00 UNALLOCATED
101 00 1 10 INSR (SIMD&FP scalar)
101 00 1 x1 UNALLOCATED
101 != 00 01 UNALLOCATED
101 != 00 1x UNALLOCATED
110 00 0 != 00 UNALLOCATED
110 00 1 10 REV (vector)
110 00 1 x1 UNALLOCATED
110 != 00 01 UNALLOCATED
110 != 00 1x UNALLOCATED
111 UNALLOCATED
0 00 DUP (indexed)
1 00 TBL

SVE unpack vector elements

These instructions are under SVE Permute Vector - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 1 0 0 U H 0 0 1 1 1 0 Zn Zd
Decode fields Instruction Details
U H
0 0 SUNPKHI, SUNPKLOSUNPKLO
0 1 SUNPKHI, SUNPKLOSUNPKHI
1 0 UUNPKHI, UUNPKLOUUNPKLO
1 1 UUNPKHI, UUNPKLOUUNPKHI

SVE Permute Predicate

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000101 op0 1 op1 010 op2 op3
Decode fields Instruction details
op0 op1 op2 op3
00 1000x 0000 0 SVE unpack predicate elements
01 1000x 0000 0 UNALLOCATED
10 1000x 0000 0 UNALLOCATED
11 1000x 0000 0 UNALLOCATED
0xxxx xxx0 0 SVE permute predicate elements
0xxxx xxx1 0 UNALLOCATED
10100 0000 0 REV (predicate)
10101 0000 0 UNALLOCATED
10x0x 1000 0 UNALLOCATED
10x0x x100 0 UNALLOCATED
10x0x xx10 0 UNALLOCATED
10x0x xxx1 0 UNALLOCATED
10x1x 0 UNALLOCATED
11xxx 0 UNALLOCATED
1 UNALLOCATED

SVE unpack predicate elements

These instructions are under SVE Permute Predicate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 H 0 1 0 0 0 0 0 Pn 0 Pd
Decode fields Instruction Details
H
0 PUNPKHI, PUNPKLOPUNPKLO
1 PUNPKHI, PUNPKLOPUNPKHI

SVE permute predicate elements

These instructions are under SVE Permute Predicate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 Pm 0 1 0 opc H 0 Pn 0 Pd
Decode fields Instruction Details
opc H
00 0 ZIP1, ZIP2 (predicates)ZIP1
00 1 ZIP1, ZIP2 (predicates)ZIP2
01 0 UZP1, UZP2 (predicates)UZP1
01 1 UZP1, UZP2 (predicates)UZP2
10 0 TRN1, TRN2 (predicates)TRN1
10 1 TRN1, TRN2 (predicates)TRN2
11 UNALLOCATED

SVE permute vector elements

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 Zm 0 1 1 opc Zn Zd
Decode fields Instruction Details
opc
000 ZIP1, ZIP2 (vectors)ZIP1
001 ZIP1, ZIP2 (vectors)ZIP2
010 UZP1, UZP2 (vectors)UZP1
011 UZP1, UZP2 (vectors)UZP2
100 TRN1, TRN2 (vectors)TRN1
101 TRN1, TRN2 (vectors)TRN2
11x UNALLOCATED

SVE Permute Vector - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000101 op0 1 op1 op2 10 op3
Decode fields Instruction details
op0 op1 op2 op3
0 0 0001 0 UNALLOCATED
1 0 0001 0 COMPACT
0 0000 0 CPY (SIMD&FP scalar)
0 000x 1 SVE extract element to general register
0 001x 0 SVE extract element to SIMD&FP scalar register
0 01xx 0 SVE reverse within elements
0 01xx 1 UNALLOCATED
0 1000 1 CPY (scalar)
0 1001 1 UNALLOCATED
0 100x 0 SVE conditionally broadcast element to vector
0 101x 0 SVE conditionally extract element to SIMD&FP scalar
0 1100 0 SPLICE
0 1100 1 UNALLOCATED
0 11!= 00 UNALLOCATED
0 x01x 1 UNALLOCATED
1 000x 0 UNALLOCATED
1 000x 1 SVE conditionally extract element to general register
1 != 000x UNALLOCATED

SVE extract element to general register

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 0 0 0 B 1 0 1 Pg Zn Rd
Decode fields Instruction Details
B
0 LASTA (scalar)
1 LASTB (scalar)

SVE extract element to SIMD&FP scalar register

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 0 0 1 B 1 0 0 Pg Zn Vd
Decode fields Instruction Details
B
0 LASTA (SIMD&FP scalar)
1 LASTB (SIMD&FP scalar)

SVE reverse within elements

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 0 1 opc 1 0 0 Pg Zn Zd
Decode fields Instruction Details
opc
00 REVB, REVH, REVWREVB
01 REVB, REVH, REVWREVH
10 REVB, REVH, REVWREVW
11 RBIT

SVE conditionally broadcast element to vector

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 1 0 0 B 1 0 0 Pg Zm Zdn
Decode fields Instruction Details
B
0 CLASTA (vectors)
1 CLASTB (vectors)

SVE conditionally extract element to SIMD&FP scalar

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 0 1 0 1 B 1 0 0 Pg Zm Vdn
Decode fields Instruction Details
B
0 CLASTA (SIMD&FP scalar)
1 CLASTB (SIMD&FP scalar)

SVE conditionally extract element to general register

These instructions are under SVE Permute Vector - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 size 1 1 0 0 0 B 1 0 1 Pg Zm Rdn
Decode fields Instruction Details
B
0 CLASTA (scalar)
1 CLASTB (scalar)

SVE Permute Vector - Extract

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000001010 op0 1 000
Decode fields Instruction details
op0
0 EXT
1 UNALLOCATED

SVE Integer Compare - Vectors

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100100 0 op0
Decode fields Instruction details
op0
0 SVE integer compare vectors
1 SVE integer compare with wide elements

SVE integer compare vectors

These instructions are under SVE Integer Compare - Vectors.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 0 size 0 Zm op 0 o2 Pg Zn ne Pd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (vectors)CMPHS
0 0 1 CMP<cc> (vectors)CMPHI
0 1 0 CMP<cc> (wide elements)CMPEQ
0 1 1 CMP<cc> (wide elements)CMPNE
1 0 0 CMP<cc> (vectors)CMPGE
1 0 1 CMP<cc> (vectors)CMPGT
1 1 0 CMP<cc> (vectors)CMPEQ
1 1 1 CMP<cc> (vectors)CMPNE

SVE integer compare with wide elements

These instructions are under SVE Integer Compare - Vectors.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 0 size 0 Zm U 1 lt Pg Zn ne Pd

SVE integer compare with unsigned immediate

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 0 size 1 imm7 lt Pg Zn ne Pd
Decode fields Instruction Details
lt ne
0 0 CMP<cc> (immediate)CMPHS
0 1 CMP<cc> (immediate)CMPHI
1 0 CMP<cc> (immediate)CMPLO
1 1 CMP<cc> (immediate)CMPLS

SVE integer compare with signed immediate

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 0 imm5 op 0 o2 Pg Zn ne Pd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (immediate)CMPGE
0 0 1 CMP<cc> (immediate)CMPGT
0 1 0 CMP<cc> (immediate)CMPLT
0 1 1 CMP<cc> (immediate)CMPLE
1 0 0 CMP<cc> (immediate)CMPEQ
1 0 1 CMP<cc> (immediate)CMPNE
1 1 UNALLOCATED

SVE predicate logical operations

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 0 Pm 0 1 Pg o2 Pn o3 Pd

SVE Propagate Break

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 00 11 op0
Decode fields Instruction details
op0
0 SVE propagate break from previous partition
1 UNALLOCATED

SVE propagate break from previous partition

These instructions are under SVE Propagate Break.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 0 Pm 1 1 Pg 0 Pn B Pd

SVE Partition Break

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 op0 01 op1 01 op2 op3
Decode fields Instruction details
op0 op1 op2 op3
0 1000 0 0 SVE propagate break to next partition
0 1000 0 1 UNALLOCATED
0 x000 1 UNALLOCATED
0 x1xx UNALLOCATED
0 xx1x UNALLOCATED
0 xxx1 UNALLOCATED
1 0000 1 UNALLOCATED
1 != 0000 UNALLOCATED
0000 0 SVE partition break condition

SVE propagate break to next partition

These instructions are under SVE Partition Break.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 0 S 0 1 1 0 0 0 0 1 Pg 0 Pn 0 Pdm

SVE partition break condition

These instructions are under SVE Partition Break.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 B S 0 1 0 0 0 0 0 1 Pg 0 Pn M Pd

SVE Predicate Misc

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 01 op0 11 op1 op2 op3 op4
Decode fields Instruction details
op0 op1 op2 op3 op4
0000 x0 0 SVE predicate test
0100 x0 0 UNALLOCATED
0x10 x0 0 UNALLOCATED
0xx1 x0 0 UNALLOCATED
0xxx x1 0 UNALLOCATED
1000 000 00 0 SVE predicate first active
1000 000 != 00 0 UNALLOCATED
1000 100 10 0000 0 SVE predicate zero
1000 100 10 != 0000 0 UNALLOCATED
1000 110 00 0 SVE predicate read from FFR (predicated)
1001 000 0x 0 UNALLOCATED
1001 000 10 0 PNEXT
1001 000 11 0 UNALLOCATED
1001 100 10 0 UNALLOCATED
1001 110 00 0000 0 SVE predicate read from FFR (unpredicated)
1001 110 00 != 0000 0 UNALLOCATED
100x 010 0 UNALLOCATED
100x 100 0x 0 SVE predicate initialize
100x 100 11 0 UNALLOCATED
100x 110 != 00 0 UNALLOCATED
100x xx1 0 UNALLOCATED
110x 0 UNALLOCATED
1x1x 0 UNALLOCATED
1 UNALLOCATED

SVE predicate test

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 1 0 0 0 0 1 1 Pg 0 Pn 0 opc2
Decode fields Instruction Details
op S opc2
0 0 UNALLOCATED
0 1 0000 PTEST
0 1 0001 UNALLOCATED
0 1 001x UNALLOCATED
0 1 01xx UNALLOCATED
0 1 1xxx UNALLOCATED
1 UNALLOCATED

SVE predicate first active

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 1 1 0 0 0 1 1 0 0 0 0 0 Pg 0 Pdn
Decode fields Instruction Details
op S
0 0 UNALLOCATED
0 1 PFIRST
1 UNALLOCATED

SVE predicate zero

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 1 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 Pd
Decode fields Instruction Details
op S
0 0 PFALSE
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate read from FFR (predicated)

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 1 1 0 0 0 1 1 1 1 0 0 0 Pg 0 Pd
Decode fields Instruction Details
op S
0 0 RDFFR, RDFFRS (predicated)not setting the condition flags
0 1 RDFFR, RDFFRS (predicated)setting the condition flags
1 UNALLOCATED

SVE predicate read from FFR (unpredicated)

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op S 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Pd
Decode fields Instruction Details
op S
0 0 RDFFR (unpredicated)
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate initialize

These instructions are under SVE Predicate Misc.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 0 1 1 0 0 S 1 1 1 0 0 0 pattern 0 Pd

SVE Integer Compare - Scalars

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 1 00 op0 op1 op2
Decode fields Instruction details
op0 op1 op2
0 SVE integer compare scalar count and limit
1 000 0000 SVE conditionally terminate scalars
1 000 != 0000 UNALLOCATED
1 != 000 UNALLOCATED

SVE integer compare scalar count and limit

These instructions are under SVE Integer Compare - Scalars.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 Rm 0 0 0 sf U lt Rn eq Pd
Decode fields Instruction Details
U lt eq
0 UNALLOCATED
0 1 0 WHILELT
0 1 1 WHILELE
1 1 0 WHILELO
1 1 1 WHILELS

SVE conditionally terminate scalars

These instructions are under SVE Integer Compare - Scalars.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 op sz 1 Rm 0 0 1 0 0 0 Rn ne 0 0 0 0
Decode fields Instruction Details
op ne
0 UNALLOCATED
1 0 CTERMEQ, CTERMNECTERMEQ
1 1 CTERMEQ, CTERMNECTERMNE

SVE Integer Wide Immediate - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 1 op0 op1 11

SVE integer add/subtract immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 0 opc 1 1 sh imm8 Zdn
Decode fields Instruction Details
opc
000 ADD (immediate)
001 SUB (immediate)
010 UNALLOCATED
011 SUBR (immediate)
100 SQADD (immediate)
101 UQADD (immediate)
110 SQSUB (immediate)
111 UQSUB (immediate)

SVE integer min/max immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 1 opc 1 1 o2 imm8 Zdn
Decode fields Instruction Details
opc o2
0xx 1 UNALLOCATED
000 0 SMAX (immediate)
001 0 UMAX (immediate)
010 0 SMIN (immediate)
011 0 UMIN (immediate)
1xx UNALLOCATED

SVE integer multiply immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 1 0 opc 1 1 o2 imm8 Zdn
Decode fields Instruction Details
opc o2
000 0 MUL (immediate)
000 1 UNALLOCATED
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE broadcast integer immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 1 1 opc 0 1 1 sh imm8 Zd
Decode fields Instruction Details
opc
00 DUP (immediate)
01 UNALLOCATED
1x UNALLOCATED

SVE broadcast floating-point immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 1 1 opc 1 1 1 o2 imm8 Zd
Decode fields Instruction Details
opc o2
00 0 FDUP
00 1 UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE predicate count

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 0 opc 1 0 Pg o2 Pn Rd
Decode fields Instruction Details
opc o2
000 0 CNTP
000 1 UNALLOCATED
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE Inc/Dec by Predicate Count

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 101 op0 1000 op1

SVE saturating inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 1 0 D U 1 0 0 0 0 opc Pg Zdn
Decode fields Instruction Details
D U opc
01 UNALLOCATED
1x UNALLOCATED
0 0 00 SQINCP (vector)
0 1 00 UQINCP (vector)
1 0 00 SQDECP (vector)
1 1 00 UQDECP (vector)

SVE saturating inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 1 0 D U 1 0 0 0 1 sf op Pg Rdn
Decode fields Instruction Details
D U sf op
1 UNALLOCATED
0 0 0 0 SQINCP (scalar)32-bit
0 0 1 0 SQINCP (scalar)64-bit
0 1 0 0 UQINCP (scalar)32-bit
0 1 1 0 UQINCP (scalar)64-bit
1 0 0 0 SQDECP (scalar)32-bit
1 0 1 0 SQDECP (scalar)64-bit
1 1 0 0 UQDECP (scalar)32-bit
1 1 1 0 UQDECP (scalar)64-bit

SVE inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 1 1 op D 1 0 0 0 0 opc2 Pg Zdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (vector)
0 1 00 DECP (vector)
1 UNALLOCATED

SVE inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 size 1 0 1 1 op D 1 0 0 0 1 opc2 Pg Rdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (scalar)
0 1 00 DECP (scalar)
1 UNALLOCATED

SVE Write FFR

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00100101 101 op0 op1 1001 op2 op3 op4
Decode fields Instruction details
op0 op1 op2 op3 op4
0 00 000 00000 SVE FFR write from predicate
1 00 000 0000 00000 SVE FFR initialise
1 00 000 1xxx 00000 UNALLOCATED
1 00 000 x1xx 00000 UNALLOCATED
1 00 000 xx1x 00000 UNALLOCATED
1 00 000 xxx1 00000 UNALLOCATED
00 000 != 00000 UNALLOCATED
00 != 000 UNALLOCATED
!= 00 UNALLOCATED

SVE FFR write from predicate

These instructions are under SVE Write FFR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 opc 1 0 1 0 0 0 1 0 0 1 0 0 0 Pn 0 0 0 0 0
Decode fields Instruction Details
opc
00 WRFFR
01 UNALLOCATED
1x UNALLOCATED

SVE FFR initialise

These instructions are under SVE Write FFR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 1 0 1 opc 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Decode fields Instruction Details
opc
00 SETFFR
01 UNALLOCATED
1x UNALLOCATED

SVE Integer Multiply-Add - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01000100 0 0 op0
Decode fields Instruction details
op0
0000 SVE integer dot product (unpredicated)
!= 0000 UNALLOCATED

SVE integer dot product (unpredicated)

These instructions are under SVE Integer Multiply-Add - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0 size 0 Zm 0 0 0 0 0 U Zn Zda
Decode fields Instruction Details
U
0 SDOT (vectors)
1 UDOT (vectors)

SVE Multiply - Indexed

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01000100 1 op0
Decode fields Instruction details
op0
00000 SVE integer dot product (indexed)
!= 00000 UNALLOCATED

SVE integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0 size 1 opc 0 0 0 0 0 U Zn Zda
Decode fields Instruction Details
size U
0x UNALLOCATED
10 0 SDOT (indexed)32-bit
10 1 UDOT (indexed)32-bit
11 0 SDOT (indexed)64-bit
11 1 UDOT (indexed)64-bit

SVE floating-point multiply-add (indexed)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 0 size 1 opc 0 0 0 0 0 op Zn Zda

SVE floating-point complex multiply-add (indexed)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 0 size 1 opc 0 0 0 1 rot Zn Zda
Decode fields Instruction Details
size
0x UNALLOCATED
10 FCMLA (indexed)half-precision
11 FCMLA (indexed)single-precision

SVE floating-point multiply (indexed)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 0 size 1 opc 0 0 1 0 0 0 Zn Zd
Decode fields Instruction Details
size
0x FMUL (indexed)half-precision
10 FMUL (indexed)single-precision
11 FMUL (indexed)double-precision

SVE floating-point compare vectors

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 Zm op 1 o2 Pg Zn o3 Pd
Decode fields Instruction Details
op o2 o3
0 0 0 FCM<cc> (vectors)FCMGE
0 0 1 FCM<cc> (vectors)FCMGT
0 1 0 FCM<cc> (vectors)FCMEQ
0 1 1 FCM<cc> (vectors)FCMNE
1 0 0 FCM<cc> (vectors)FCMUO
1 0 1 FAC<cc>FACGE
1 1 0 UNALLOCATED
1 1 1 FAC<cc>FACGT

SVE floating-point arithmetic (unpredicated)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 Zm 0 0 0 opc Zn Zd
Decode fields Instruction Details
opc
000 FADD (vectors, unpredicated)
001 FSUB (vectors, unpredicated)
010 FMUL (vectors, unpredicated)
011 FTSMUL
10x UNALLOCATED
110 FRECPS
111 FRSQRTS

SVE Floating Point Arithmetic - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01100101 0 op0 100 op1 op2
Decode fields Instruction details
op0 op1 op2
0x SVE floating-point arithmetic (predicated)
10 000 FTMAD
10 != 000 UNALLOCATED
11 0000 SVE floating-point arithmetic with immediate (predicated)
11 != 0000 UNALLOCATED

SVE floating-point arithmetic (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 0 opc 1 0 0 Pg Zm Zdn
Decode fields Instruction Details
opc
0000 FADD (vectors, predicated)
0001 FSUB (vectors, predicated)
0010 FMUL (vectors, predicated)
0011 FSUBR (vectors)
0100 FMAXNM (vectors)
0101 FMINNM (vectors)
0110 FMAX (vectors)
0111 FMIN (vectors)
1000 FABD
1001 FSCALE
1010 FMULX
1011 UNALLOCATED
1100 FDIVR
1101 FDIV
111x UNALLOCATED

SVE floating-point arithmetic with immediate (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 1 1 opc 1 0 0 Pg 0 0 0 0 i1 Zdn

SVE Floating Point Unary Operations - Predicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01100101 0 op0 101

SVE floating-point round to integral value

These instructions are under SVE Floating Point Unary Operations - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 0 0 opc 1 0 1 Pg Zn Zd

SVE floating-point convert precision

These instructions are under SVE Floating Point Unary Operations - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 opc 0 0 1 0 opc2 1 0 1 Pg Zn Zd

SVE floating-point unary operations

These instructions are under SVE Floating Point Unary Operations - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 0 1 1 opc 1 0 1 Pg Zn Zd
Decode fields Instruction Details
opc
00 FRECPX
01 FSQRT
1x UNALLOCATED

SVE integer convert to floating-point

These instructions are under SVE Floating Point Unary Operations - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 opc 0 1 0 opc2 U 1 0 1 Pg Zn Zd
Decode fields Instruction Details
opc opc2 U
00 UNALLOCATED
01 00 UNALLOCATED
01 01 0 SCVTF16-bit to half-precision
01 01 1 UCVTF16-bit to half-precision
01 10 0 SCVTF32-bit to half-precision
01 10 1 UCVTF32-bit to half-precision
01 11 0 SCVTF64-bit to half-precision
01 11 1 UCVTF64-bit to half-precision
10 0x UNALLOCATED
10 10 0 SCVTF32-bit to single-precision
10 10 1 UCVTF32-bit to single-precision
10 11 UNALLOCATED
11 00 0 SCVTF32-bit to double-precision
11 00 1 UCVTF32-bit to double-precision
11 01 UNALLOCATED
11 10 0 SCVTF64-bit to single-precision
11 10 1 UCVTF64-bit to single-precision
11 11 0 SCVTF64-bit to double-precision
11 11 1 UCVTF64-bit to double-precision

SVE floating-point convert to integer

These instructions are under SVE Floating Point Unary Operations - Predicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 opc 0 1 1 opc2 U 1 0 1 Pg Zn Zd
Decode fields Instruction Details
opc opc2 U
00 UNALLOCATED
01 00 UNALLOCATED
01 01 0 FCVTZShalf-precision to 16-bit
01 01 1 FCVTZUhalf-precision to 16-bit
01 10 0 FCVTZShalf-precision to 32-bit
01 10 1 FCVTZUhalf-precision to 32-bit
01 11 0 FCVTZShalf-precision to 64-bit
01 11 1 FCVTZUhalf-precision to 64-bit
10 0x UNALLOCATED
10 10 0 FCVTZSsingle-precision to 32-bit
10 10 1 FCVTZUsingle-precision to 32-bit
10 11 UNALLOCATED
11 00 0 FCVTZSdouble-precision to 32-bit
11 00 1 FCVTZUdouble-precision to 32-bit
11 01 UNALLOCATED
11 10 0 FCVTZSsingle-precision to 64-bit
11 10 1 FCVTZUsingle-precision to 64-bit
11 11 0 FCVTZSdouble-precision to 64-bit
11 11 1 FCVTZUdouble-precision to 64-bit

SVE floating-point recursive reduction

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 0 0 opc 0 0 1 Pg Zn Vd
Decode fields Instruction Details
opc
000 FADDV
001 UNALLOCATED
01x UNALLOCATED
100 FMAXNMV
101 FMINNMV
110 FMAXV
111 FMINV

SVE Floating Point Unary Operations - Unpredicated

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01100101 001 0011 op0
Decode fields Instruction details
op0
00 SVE floating-point reciprocal estimate (unpredicated)
!= 00 UNALLOCATED

SVE floating-point reciprocal estimate (unpredicated)

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 0 1 opc 0 0 1 1 0 0 Zn Zd
Decode fields Instruction Details
opc
0xx UNALLOCATED
10x UNALLOCATED
110 FRECPE
111 FRSQRTE

SVE Floating Point Compare - with Zero

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01100101 010 op0 001
Decode fields Instruction details
op0
0 SVE floating-point compare with zero
1 UNALLOCATED

SVE floating-point compare with zero

These instructions are under SVE Floating Point Compare - with Zero.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 1 0 0 eq lt 0 0 1 Pg Zn ne Pd
Decode fields Instruction Details
eq lt ne
0 0 0 FCM<cc> (zero)FCMGE
0 0 1 FCM<cc> (zero)FCMGT
0 1 0 FCM<cc> (zero)FCMLT
0 1 1 FCM<cc> (zero)FCMLE
1 1 UNALLOCATED
1 0 0 FCM<cc> (zero)FCMEQ
1 1 0 FCM<cc> (zero)FCMNE

SVE floating-point serial reduction (predicated)

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 0 1 1 opc 0 0 1 Pg Zm Vdn
Decode fields Instruction Details
opc
000 FADDA
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE Floating Point Multiply-Add

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
01100101 1 op0

SVE floating-point multiply-accumulate writing addend

These instructions are under SVE Floating Point Multiply-Add.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 1 Zm 0 opc Pg Zn Zda
Decode fields Instruction Details
opc
00 FMLA (vectors)
01 FMLS (vectors)
10 FNMLA
11 FNMLS

SVE floating-point multiply-accumulate writing multiplicand

These instructions are under SVE Floating Point Multiply-Add.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1 size 1 Za 1 opc Pg Zm Zdn
Decode fields Instruction Details
opc
00 FMAD
01 FMSB
10 FNMAD
11 FNMSB

SVE Memory - 32-bit Gather and Unsized Contiguous

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000010 op0 op1 op2

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 0 0 xs 1 Zm 0 msz Pg Rn 0 prfop

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 0 1 xs 1 Zm 0 U ff Pg Rn Zt

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 1 0 xs 1 Zm 0 U ff Pg Rn Zt
Decode fields Instruction Details
U ff
0 UNALLOCATED
1 0 LD1W (scalar plus vector)
1 1 LDFF1W (scalar plus vector)

SVE contiguous prefetch (scalar plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 1 1 1 imm6 0 msz Pg Rn 0 prfop

SVE contiguous prefetch (scalar plus scalar)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 msz 0 0 Rm 1 1 0 Pg Rn 0 prfop

SVE 32-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 msz 0 0 imm5 1 1 1 Pg Zn 0 prfop

SVE 32-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 msz 0 1 imm5 1 U ff Pg Zn Zt

SVE load and broadcast element

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 dtypeh 1 imm6 1 dtypel Pg Rn Zt
Decode fields Instruction Details
dtypeh dtypel
00 00 LD1RB8-bit element
00 01 LD1RB16-bit element
00 10 LD1RB32-bit element
00 11 LD1RB64-bit element
01 00 LD1RSW
01 01 LD1RH16-bit element
01 10 LD1RH32-bit element
01 11 LD1RH64-bit element
10 00 LD1RSH64-bit element
10 01 LD1RSH32-bit element
10 10 LD1RW32-bit element
10 11 LD1RW64-bit element
11 00 LD1RSB64-bit element
11 01 LD1RSB32-bit element
11 10 LD1RSB16-bit element
11 11 LD1RD

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 1 0 msz xs 0 Zm 0 U ff Pg Rn Zt
Decode fields Instruction Details
msz xs U ff Zt
00 0 0 LD1SB (scalar plus vector)
00 0 1 LDFF1SB (scalar plus vector)
00 1 0 LD1B (scalar plus vector)
00 1 1 LDFF1B (scalar plus vector)
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 UNALLOCATED
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)
11 0 1 UNALLOCATED
11 0 0 0 1xxxx UNALLOCATED
11 1 1xxxx UNALLOCATED

SVE Memory - Contiguous Load

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1010010 op0 op1

SVE load and broadcast quadword (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0 1 0 msz ssz 0 imm4 0 0 1 Pg Rn Zt
Decode fields Instruction Details
msz ssz
01 UNALLOCATED
1x UNALLOCATED
00 00 LD1RQB (scalar plus immediate)
01 00 LD1RQH (scalar plus immediate)
10 00 LD1RQW (scalar plus immediate)
11 00 LD1RQD (scalar plus immediate)


SVE load multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0 1 0 msz num 0 imm4 1 1 1 Pg Rn Zt

SVE contiguous non-fault load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0 1 0 dtype 1 imm4 1 0 1 Pg Rn Zt
Decode fields Instruction Details
dtype
0000 LDNF1B8-bit element
0001 LDNF1B16-bit element
0010 LDNF1B32-bit element
0011 LDNF1B64-bit element
0100 LDNF1SW
0101 LDNF1H16-bit element
0110 LDNF1H32-bit element
0111 LDNF1H64-bit element
1000 LDNF1SH64-bit element
1001 LDNF1SH32-bit element
1010 LDNF1W32-bit element
1011 LDNF1W64-bit element
1100 LDNF1SB64-bit element
1101 LDNF1SB32-bit element
1110 LDNF1SB16-bit element
1111 LDNF1D

SVE load and broadcast quadword (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0 1 0 msz ssz Rm 0 0 0 Pg Rn Zt
Decode fields Instruction Details
msz ssz
01 UNALLOCATED
1x UNALLOCATED
00 00 LD1RQB (scalar plus scalar)
01 00 LD1RQH (scalar plus scalar)
10 00 LD1RQW (scalar plus scalar)
11 00 LD1RQD (scalar plus scalar)



SVE load multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 0 1 0 msz num Rm 1 1 0 Pg Rn Zt

SVE Memory - 64-bit Gather

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1100010 op0 op1 op2

SVE 64-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz 0 0 imm5 1 1 1 Pg Zn 0 prfop

SVE 64-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz 0 1 imm5 1 U ff Pg Zn Zt

SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz 1 0 Zm 1 U ff Pg Rn Zt

SVE 64-bit gather load (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz 1 1 Zm 1 U ff Pg Rn Zt

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz xs 0 Zm 0 U ff Pg Rn Zt

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 1 0 msz xs 1 Zm 0 U ff Pg Rn Zt

SVE Memory - Store

These instructions are under SVE encodings.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1110010 op0 op1 op2

SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 0 0 Zm 1 0 1 Pg Rn Zt

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 0 0 Zm 1 xs 0 Pg Rn Zt

SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 0 1 Zm 1 0 1 Pg Rn Zt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 0 1 Zm 1 xs 0 Pg Rn Zt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 1 0 imm5 1 0 1 Pg Zn Zt

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 1 0 Zm 1 xs 0 Pg Rn Zt
Decode fields Instruction Details
msz
00 ST1B (scalar plus vector)
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE 32-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 1 1 imm5 1 0 1 Pg Zn Zt
Decode fields Instruction Details
msz
00 ST1B (vector plus immediate)
01 ST1H (vector plus immediate)
10 ST1W (vector plus immediate)
11 UNALLOCATED

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz 1 1 Zm 1 xs 0 Pg Rn Zt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE contiguous store (scalar plus immediate)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz size 0 imm4 1 1 1 Pg Rn Zt

SVE store multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz num 1 imm4 1 1 1 Pg Rn Zt

SVE contiguous store (scalar plus scalar)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz size Rm 0 1 0 Pg Rn Zt
Decode fields Instruction Details
msz size
00 ST1B (scalar plus scalar)
01 ST1H (scalar plus scalar)
10 ST1W (scalar plus scalar)
11 10 UNALLOCATED
11 11 ST1D (scalar plus scalar)

SVE store multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 0 msz num Rm 0 1 1 Pg Rn Zt

Data Processing -- Immediate

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
100 op0

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op immlo 1 0 0 0 0 immhi Rd
Decode fields Instruction Details
op
0 ADR
1 ADRP

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf op S 1 0 0 0 1 0 sh imm12 Rn Rd
Decode fields Instruction Details
sf op S
0 0 0 ADD (immediate)32-bit
0 0 1 ADDS (immediate)32-bit
0 1 0 SUB (immediate)32-bit
0 1 1 SUBS (immediate)32-bit
1 0 0 ADD (immediate)64-bit
1 0 1 ADDS (immediate)64-bit
1 1 0 SUB (immediate)64-bit
1 1 1 SUBS (immediate)64-bit

Add/subtract (immediate, with tags)

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf op S 1 0 0 0 1 1 o2 uimm6 op3 uimm4 Rn Rd
Decode fields Instruction Details Architecture Version
sf op S
0 UNALLOCATED -
1 1 UNALLOCATED -
1 0 0 ADDG Armv8.5
1 1 0 SUBG Armv8.5

Logical (immediate)

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf opc 1 0 0 1 0 0 N immr imms Rn Rd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 AND (immediate)32-bit
0 01 0 ORR (immediate)32-bit
0 10 0 EOR (immediate)32-bit
0 11 0 ANDS (immediate)32-bit
1 00 AND (immediate)64-bit
1 01 ORR (immediate)64-bit
1 10 EOR (immediate)64-bit
1 11 ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf opc 1 0 0 1 0 1 hw imm16 Rd
Decode fields Instruction Details
sf opc hw
01 UNALLOCATED
0 1x UNALLOCATED
0 00 MOVN32-bit
0 10 MOVZ32-bit
0 11 MOVK32-bit
1 00 MOVN64-bit
1 10 MOVZ64-bit
1 11 MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf opc 1 0 0 1 1 0 N immr imms Rn Rd
Decode fields Instruction Details
sf opc N
11 UNALLOCATED
0 1 UNALLOCATED
0 00 0 SBFM32-bit
0 01 0 BFM32-bit
0 10 0 UBFM32-bit
1 0 UNALLOCATED
1 00 1 SBFM64-bit
1 01 1 BFM64-bit
1 10 1 UBFM64-bit

Extract

These instructions are under Data Processing -- Immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf op21 1 0 0 1 1 1 N o0 Rm imms Rn Rd
Decode fields Instruction Details
sf op21 N o0 imms
x1 UNALLOCATED
00 1 UNALLOCATED
1x UNALLOCATED
0 1xxxxx UNALLOCATED
0 1 UNALLOCATED
0 00 0 0 0xxxxx EXTR32-bit
1 0 UNALLOCATED
1 00 1 0 EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 101 op1 op2
Decode fields Instruction details
op0 op1 op2
010 0xxxxxxxxxxxxx Conditional branch (immediate)
110 00xxxxxxxxxxxx Exception generation
110 01000000110010 11111 Hints
110 01000000110011 Barriers
110 0100000xxx0100 PSTATE
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 1xxxxxxxxxxxxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 o1 imm19 o0 cond
Decode fields Instruction Details
o1 o0
0 0 B.cond
0 1 UNALLOCATED
1 UNALLOCATED

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 0 opc imm16 op2 LL
Decode fields Instruction Details
opc op2 LL
xx1 UNALLOCATED
x1x UNALLOCATED
1xx UNALLOCATED
000 000 00 UNALLOCATED
000 000 01 SVC
000 000 10 HVC
000 000 11 SMC
001 000 x1 UNALLOCATED
001 000 00 BRK
001 000 1x UNALLOCATED
010 000 x1 UNALLOCATED
010 000 00 HLT
010 000 1x UNALLOCATED
011 000 01 UNALLOCATED
011 000 1x UNALLOCATED
100 000 00 UNALLOCATED
101 000 00 UNALLOCATED
101 000 01 DCPS1
101 000 10 DCPS2
101 000 11 DCPS3
110 000 UNALLOCATED
111 000 01 UNALLOCATED
111 000 1x UNALLOCATED

Hints

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 CRm op2 1 1 1 1 1
Decode fields Instruction Details Architecture Version
CRm op2
HINT -
0000 000 NOP -
0000 001 YIELD -
0000 010 WFE -
0000 011 WFI -
0000 100 SEV -
0000 101 SEVL -
0000 111 XPACD, XPACI, XPACLRI Armv8.3
0001 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIA1716 Armv8.3
0001 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIB1716 Armv8.3
0001 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIA1716 Armv8.3
0001 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIB1716 Armv8.3
0010 000 ESB Armv8.2
0010 001 PSB CSYNC Armv8.2
0010 010 TSB CSYNC Armv8.4
0010 100 CSDB -
0011 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAZ Armv8.3
0011 001 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIASP Armv8.3
0011 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBZ Armv8.3
0011 011 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBSP Armv8.3
0011 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAZ Armv8.3
0011 101 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIASP Armv8.3
0011 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBZ Armv8.3
0011 111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBSP Armv8.3
0100 xx0 BTI Armv8.5

Barriers

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 CRm op2 Rt
Decode fields Instruction Details
CRm op2 Rt
000 UNALLOCATED
001 UNALLOCATED
010 11111 CLREX
101 11111 DMB
110 11111 ISB
111 != 11111 UNALLOCATED
111 11111 SB
!= 0x00 100 11111 DSB
0000 100 11111 SSBB
0001 011 UNALLOCATED
001x 011 UNALLOCATED
01xx 011 UNALLOCATED
0100 100 11111 PSSBB
1xxx 011 UNALLOCATED

PSTATE

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 1 0 0 0 0 0 op1 0 1 0 0 CRm op2 Rt
Decode fields Instruction Details Architecture Version
op1 op2 Rt
!= 11111 UNALLOCATED -
11111 MSR (immediate) -
000 000 11111 CFINV Armv8.4
000 001 11111 XAFlag Armv8.5
000 010 11111 AXFlag Armv8.5

System instructions

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 1 0 0 L 0 1 op1 CRn CRm op2 Rt
Decode fields Instruction Details
L
0 SYS
1 SYSL

System register move

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 0 1 0 0 L 1 o0 op1 CRn CRm op2 Rt
Decode fields Instruction Details
L
0 MSR (register)
1 MRS

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 1 1 opc op2 op3 Rn op4
Decode fields Instruction Details Architecture Version
opc op2 op3 Rn op4
!= 11111 UNALLOCATED -
0000 11111 000000 != 00000 UNALLOCATED -
0000 11111 000000 00000 BR -
0000 11111 000001 UNALLOCATED -
0000 11111 000010 != 11111 UNALLOCATED -
0000 11111 000010 11111 BRAA, BRAAZ, BRAB, BRABZkey A, zero modifier Armv8.3
0000 11111 000011 != 11111 UNALLOCATED -
0000 11111 000011 11111 BRAA, BRAAZ, BRAB, BRABZkey B, zero modifier Armv8.3
0000 11111 0001xx UNALLOCATED -
0000 11111 001xxx UNALLOCATED -
0000 11111 01xxxx UNALLOCATED -
0000 11111 1xxxxx UNALLOCATED -
0001 11111 000000 != 00000 UNALLOCATED -
0001 11111 000000 00000 BLR -
0001 11111 000001 UNALLOCATED -
0001 11111 000010 != 11111 UNALLOCATED -
0001 11111 000010 11111 BLRAA, BLRAAZ, BLRAB, BLRABZkey A, zero modifier Armv8.3
0001 11111 000011 != 11111 UNALLOCATED -
0001 11111 000011 11111 BLRAA, BLRAAZ, BLRAB, BLRABZkey B, zero modifier Armv8.3
0001 11111 0001xx UNALLOCATED -
0001 11111 001xxx UNALLOCATED -
0001 11111 01xxxx UNALLOCATED -
0001 11111 1xxxxx UNALLOCATED -
0010 11111 000000 != 00000 UNALLOCATED -
0010 11111 000000 00000 RET -
0010 11111 000001 UNALLOCATED -
0010 11111 000010 != 11111 != 11111 UNALLOCATED -
0010 11111 000010 11111 11111 RETAA, RETABRETAA Armv8.3
0010 11111 000011 != 11111 != 11111 UNALLOCATED -
0010 11111 000011 11111 11111 RETAA, RETABRETAB Armv8.3
0010 11111 0001xx UNALLOCATED -
0010 11111 001xxx UNALLOCATED -
0010 11111 01xxxx UNALLOCATED -
0010 11111 1xxxxx UNALLOCATED -
0011 11111 UNALLOCATED -
0100 11111 000000 != 11111 != 00000 UNALLOCATED -
0100 11111 000000 != 11111 00000 UNALLOCATED -
0100 11111 000000 11111 != 00000 UNALLOCATED -
0100 11111 000000 11111 00000 ERET -
0100 11111 000001 UNALLOCATED -
0100 11111 000010 != 11111 != 11111 UNALLOCATED -
0100 11111 000010 != 11111 11111 UNALLOCATED -
0100 11111 000010 11111 != 11111 UNALLOCATED -
0100 11111 000010 11111 11111 ERETAA, ERETABERETAA Armv8.3
0100 11111 000011 != 11111 != 11111 UNALLOCATED -
0100 11111 000011 != 11111 11111 UNALLOCATED -
0100 11111 000011 11111 != 11111 UNALLOCATED -
0100 11111 000011 11111 11111 ERETAA, ERETABERETAB Armv8.3
0100 11111 0001xx UNALLOCATED -
0100 11111 001xxx UNALLOCATED -
0100 11111 01xxxx UNALLOCATED -
0100 11111 1xxxxx UNALLOCATED -
0101 11111 != 000000 UNALLOCATED -
0101 11111 000000 != 11111 != 00000 UNALLOCATED -
0101 11111 000000 != 11111 00000 UNALLOCATED -
0101 11111 000000 11111 != 00000 UNALLOCATED -
0101 11111 000000 11111 00000 DRPS -
011x 11111 UNALLOCATED -
1000 11111 00000x UNALLOCATED -
1000 11111 000010 BRAA, BRAAZ, BRAB, BRABZkey A, register modifier Armv8.3
1000 11111 000011 BRAA, BRAAZ, BRAB, BRABZkey B, register modifier Armv8.3
1000 11111 0001xx UNALLOCATED -
1000 11111 001xxx UNALLOCATED -
1000 11111 01xxxx UNALLOCATED -
1000 11111 1xxxxx UNALLOCATED -
1001 11111 00000x UNALLOCATED -
1001 11111 000010 BLRAA, BLRAAZ, BLRAB, BLRABZkey A, register modifier Armv8.3
1001 11111 000011 BLRAA, BLRAAZ, BLRAB, BLRABZkey B, register modifier Armv8.3
1001 11111 0001xx UNALLOCATED -
1001 11111 001xxx UNALLOCATED -
1001 11111 01xxxx UNALLOCATED -
1001 11111 1xxxxx UNALLOCATED -
101x 11111 UNALLOCATED -
11xx 11111 UNALLOCATED -

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op 0 0 1 0 1 imm26
Decode fields Instruction Details
op
0 B
1 BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sf 0 1 1 0 1 0 op imm19 Rt
Decode fields Instruction Details
sf op
0 0 CBZ32-bit
0 1 CBNZ32-bit
1 0 CBZ64-bit
1 1 CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b5 0 1 1 0 1 1 op b40 imm14 Rt
Decode fields Instruction Details
op
0 TBZ
1 TBNZ

Loads and Stores

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 1 op1 0 op2 op3 op4
Decode fields Instruction details
op0 op1 op2 op3 op4
0x00 1 00 000000 Advanced SIMD load/store multiple structures
0x00 1 01 0xxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0x 1xxxxx UNALLOCATED
0x00 1 10 x00000 Advanced SIMD load/store single structure
0x00 1 11 Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0 x1xxxx UNALLOCATED
0x00 1 x0 xx1xxx UNALLOCATED
0x00 1 x0 xxx1xx UNALLOCATED
0x00 1 x0 xxxx1x UNALLOCATED
0x00 1 x0 xxxxx1 UNALLOCATED
1101 0 1x 1xxxxx Load/store memory tags
1x00 1 UNALLOCATED
xx00 0 0x Load/store exclusive
xx01 0 1x 0xxxxx 00 LDAPR/STLR (unscaled immediate)
xx01 0x Load register (literal)
xx10 00 Load/store no-allocate pair (offset)
xx10 01 Load/store register pair (post-indexed)
xx10 10 Load/store register pair (offset)
xx10 11 Load/store register pair (pre-indexed)
xx11 0x 0xxxxx 00 Load/store register (unscaled immediate)
xx11 0x 0xxxxx 01 Load/store register (immediate post-indexed)
xx11 0x 0xxxxx 10 Load/store register (unprivileged)
xx11 0x 0xxxxx 11 Load/store register (immediate pre-indexed)
xx11 0x 1xxxxx 00 Atomic memory operations
xx11 0x 1xxxxx 10 Load/store register (register offset)
xx11 0x 1xxxxx x1 Load/store register (pac)
xx11 1x Load/store register (unsigned immediate)

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 0 0 0 L 0 0 0 0 0 0 opcode size Rn Rt
Decode fields Instruction Details
L opcode
0 0000 ST4 (multiple structures)
0 0001 UNALLOCATED
0 0010 ST1 (multiple structures)four registers
0 0011 UNALLOCATED
0 0100 ST3 (multiple structures)
0 0101 UNALLOCATED
0 0110 ST1 (multiple structures)three registers
0 0111 ST1 (multiple structures)one register
0 1000 ST2 (multiple structures)
0 1001 UNALLOCATED
0 1010 ST1 (multiple structures)two registers
0 1011 UNALLOCATED
0 11xx UNALLOCATED
1 0000 LD4 (multiple structures)
1 0001 UNALLOCATED
1 0010 LD1 (multiple structures)four registers
1 0011 UNALLOCATED
1 0100 LD3 (multiple structures)
1 0101 UNALLOCATED
1 0110 LD1 (multiple structures)three registers
1 0111 LD1 (multiple structures)one register
1 1000 LD2 (multiple structures)
1 1001 UNALLOCATED
1 1010 LD1 (multiple structures)two registers
1 1011 UNALLOCATED
1 11xx UNALLOCATED

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 0 0 1 L 0 Rm opcode size Rn Rt
Decode fields Instruction Details
L Rm opcode
0 0001 UNALLOCATED
0 0011 UNALLOCATED
0 0101 UNALLOCATED
0 1001 UNALLOCATED
0 1011 UNALLOCATED
0 11xx UNALLOCATED
0 != 11111 0000 ST4 (multiple structures)register offset
0 != 11111 0010 ST1 (multiple structures)four registers, register offset
0 != 11111 0100 ST3 (multiple structures)register offset
0 != 11111 0110 ST1 (multiple structures)three registers, register offset
0 != 11111 0111 ST1 (multiple structures)one register, register offset
0 != 11111 1000 ST2 (multiple structures)register offset
0 != 11111 1010 ST1 (multiple structures)two registers, register offset
0 11111 0000 ST4 (multiple structures)immediate offset
0 11111 0010 ST1 (multiple structures)four registers, immediate offset
0 11111 0100 ST3 (multiple structures)immediate offset
0 11111 0110 ST1 (multiple structures)three registers, immediate offset
0 11111 0111 ST1 (multiple structures)one register, immediate offset
0 11111 1000 ST2 (multiple structures)immediate offset
0 11111 1010 ST1 (multiple structures)two registers, immediate offset
1 0001 UNALLOCATED
1 0011 UNALLOCATED
1 0101 UNALLOCATED
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 11xx UNALLOCATED
1 != 11111 0000 LD4 (multiple structures)register offset
1 != 11111 0010 LD1 (multiple structures)four registers, register offset
1 != 11111 0100 LD3 (multiple structures)register offset
1 != 11111 0110 LD1 (multiple structures)three registers, register offset
1 != 11111 0111 LD1 (multiple structures)one register, register offset
1 != 11111 1000 LD2 (multiple structures)register offset
1 != 11111 1010 LD1 (multiple structures)two registers, register offset
1 11111 0000 LD4 (multiple structures)immediate offset
1 11111 0010 LD1 (multiple structures)four registers, immediate offset
1 11111 0100 LD3 (multiple structures)immediate offset
1 11111 0110 LD1 (multiple structures)three registers, immediate offset
1 11111 0111 LD1 (multiple structures)one register, immediate offset
1 11111 1000 LD2 (multiple structures)immediate offset
1 11111 1010 LD1 (multiple structures)two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 0 1 0 L R 0 0 0 0 0 opcode S size Rn Rt
Decode fields Instruction Details
L R opcode S size
0 11x UNALLOCATED
0 0 000 ST1 (single structure)8-bit
0 0 001 ST3 (single structure)8-bit
0 0 010 x0 ST1 (single structure)16-bit
0 0 010 x1 UNALLOCATED
0 0 011 x0 ST3 (single structure)16-bit
0 0 011 x1 UNALLOCATED
0 0 100 00 ST1 (single structure)32-bit
0 0 100 1x UNALLOCATED
0 0 100 0 01 ST1 (single structure)64-bit
0 0 100 1 01 UNALLOCATED
0 0 101 00 ST3 (single structure)32-bit
0 0 101 10 UNALLOCATED
0 0 101 0 01 ST3 (single structure)64-bit
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 1 000 ST2 (single structure)8-bit
0 1 001 ST4 (single structure)8-bit
0 1 010 x0 ST2 (single structure)16-bit
0 1 010 x1 UNALLOCATED
0 1 011 x0 ST4 (single structure)16-bit
0 1 011 x1 UNALLOCATED
0 1 100 00 ST2 (single structure)32-bit
0 1 100 10 UNALLOCATED
0 1 100 0 01 ST2 (single structure)64-bit
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 00 ST4 (single structure)32-bit
0 1 101 10 UNALLOCATED
0 1 101 0 01 ST4 (single structure)64-bit
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
1 0 000 LD1 (single structure)8-bit
1 0 001 LD3 (single structure)8-bit
1 0 010 x0 LD1 (single structure)16-bit
1 0 010 x1 UNALLOCATED
1 0 011 x0 LD3 (single structure)16-bit
1 0 011 x1 UNALLOCATED
1 0 100 00 LD1 (single structure)32-bit
1 0 100 1x UNALLOCATED
1 0 100 0 01 LD1 (single structure)64-bit
1 0 100 1 01 UNALLOCATED
1 0 101 00 LD3 (single structure)32-bit
1 0 101 10 UNALLOCATED
1 0 101 0 01 LD3 (single structure)64-bit
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 0 LD1R
1 0 110 1 UNALLOCATED
1 0 111 0 LD3R
1 0 111 1 UNALLOCATED
1 1 000 LD2 (single structure)8-bit
1 1 001 LD4 (single structure)8-bit
1 1 010 x0 LD2 (single structure)16-bit
1 1 010 x1 UNALLOCATED
1 1 011 x0 LD4 (single structure)16-bit
1 1 011 x1 UNALLOCATED
1 1 100 00 LD2 (single structure)32-bit
1 1 100 10 UNALLOCATED
1 1 100 0 01 LD2 (single structure)64-bit
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 00 LD4 (single structure)32-bit
1 1 101 10 UNALLOCATED
1 1 101 0 01 LD4 (single structure)64-bit
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 0 LD2R
1 1 110 1 UNALLOCATED
1 1 111 0 LD4R
1 1 111 1 UNALLOCATED

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Q 0 0 1 1 0 1 1 L R Rm opcode S size Rn Rt
Decode fields Instruction Details
L R Rm opcode S size
0 11x UNALLOCATED
0 0 010 x1 UNALLOCATED
0 0 011 x1 UNALLOCATED
0 0 100 1x UNALLOCATED
0 0 100 1 01 UNALLOCATED
0 0 101 10 UNALLOCATED
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 0 != 11111 000 ST1 (single structure)8-bit, register offset
0 0 != 11111 001 ST3 (single structure)8-bit, register offset
0 0 != 11111 010 x0 ST1 (single structure)16-bit, register offset
0 0 != 11111 011 x0 ST3 (single structure)16-bit, register offset
0 0 != 11111 100 00 ST1 (single structure)32-bit, register offset
0 0 != 11111 100 0 01 ST1 (single structure)64-bit, register offset
0 0 != 11111 101 00 ST3 (single structure)32-bit, register offset
0 0 != 11111 101 0 01 ST3 (single structure)64-bit, register offset
0 0 11111 000 ST1 (single structure)8-bit, immediate offset
0 0 11111 001 ST3 (single structure)8-bit, immediate offset
0 0 11111 010 x0 ST1 (single structure)16-bit, immediate offset
0 0 11111 011 x0 ST3 (single structure)16-bit, immediate offset
0 0 11111 100 00 ST1 (single structure)32-bit, immediate offset
0 0 11111 100 0 01 ST1 (single structure)64-bit, immediate offset
0 0 11111 101 00 ST3 (single structure)32-bit, immediate offset
0 0 11111 101 0 01 ST3 (single structure)64-bit, immediate offset
0 1 010 x1 UNALLOCATED
0 1 011 x1 UNALLOCATED
0 1 100 10 UNALLOCATED
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 10 UNALLOCATED
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
0 1 != 11111 000 ST2 (single structure)8-bit, register offset
0 1 != 11111 001 ST4 (single structure)8-bit, register offset
0 1 != 11111 010 x0 ST2 (single structure)16-bit, register offset
0 1 != 11111 011 x0 ST4 (single structure)16-bit, register offset
0 1 != 11111 100 00 ST2 (single structure)32-bit, register offset
0 1 != 11111 100 0 01 ST2 (single structure)64-bit, register offset
0 1 != 11111 101 00 ST4 (single structure)32-bit, register offset
0 1 != 11111 101 0 01 ST4 (single structure)64-bit, register offset
0 1 11111 000 ST2 (single structure)8-bit, immediate offset
0 1 11111 001 ST4 (single structure)8-bit, immediate offset
0 1 11111 010 x0 ST2 (single structure)16-bit, immediate offset
0 1 11111 011 x0 ST4 (single structure)16-bit, immediate offset
0 1 11111 100 00 ST2 (single structure)32-bit, immediate offset
0 1 11111 100 0 01 ST2 (single structure)64-bit, immediate offset
0 1 11111 101 00 ST4 (single structure)32-bit, immediate offset
0 1 11111 101 0 01 ST4 (single structure)64-bit, immediate offset
1 0 010 x1 UNALLOCATED
1 0 011 x1 UNALLOCATED
1 0 100 1x UNALLOCATED
1 0 100 1 01 UNALLOCATED
1 0 101 10 UNALLOCATED
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 1 UNALLOCATED
1 0 111 1 UNALLOCATED
1 0 != 11111 000 LD1 (single structure)8-bit, register offset
1 0 != 11111 001 LD3 (single structure)8-bit, register offset
1 0 != 11111 010 x0 LD1 (single structure)16-bit, register offset
1 0 != 11111 011 x0 LD3 (single structure)16-bit, register offset
1 0 != 11111 100 00 LD1 (single structure)32-bit, register offset
1 0 != 11111 100 0 01 LD1 (single structure)64-bit, register offset
1 0 != 11111 101 00 LD3 (single structure)32-bit, register offset
1 0 != 11111 101 0 01 LD3 (single structure)64-bit, register offset
1 0 != 11111 110 0 LD1Rregister offset
1 0 != 11111 111 0 LD3Rregister offset
1 0 11111 000 LD1 (single structure)8-bit, immediate offset
1 0 11111 001 LD3 (single structure)8-bit, immediate offset
1 0 11111 010 x0 LD1 (single structure)16-bit, immediate offset
1 0 11111 011 x0 LD3 (single structure)16-bit, immediate offset
1 0 11111 100 00 LD1 (single structure)32-bit, immediate offset
1 0 11111 100 0 01 LD1 (single structure)64-bit, immediate offset
1 0 11111 101 00 LD3 (single structure)32-bit, immediate offset
1 0 11111 101 0 01 LD3 (single structure)64-bit, immediate offset
1 0 11111 110 0 LD1Rimmediate offset
1 0 11111 111 0 LD3Rimmediate offset
1 1 010 x1 UNALLOCATED
1 1 011 x1 UNALLOCATED
1 1 100 10 UNALLOCATED
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 10 UNALLOCATED
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 1 UNALLOCATED
1 1 111 1 UNALLOCATED
1 1 != 11111 000 LD2 (single structure)8-bit, register offset
1 1 != 11111 001 LD4 (single structure)8-bit, register offset
1 1 != 11111 010 x0 LD2 (single structure)16-bit, register offset
1 1 != 11111 011 x0 LD4 (single structure)16-bit, register offset
1 1 != 11111 100 00 LD2 (single structure)32-bit, register offset
1 1 != 11111 100 0 01 LD2 (single structure)64-bit, register offset
1 1 != 11111 101 00 LD4 (single structure)32-bit, register offset
1 1 != 11111 101 0 01 LD4 (single structure)64-bit, register offset
1 1 != 11111 110 0 LD2Rregister offset
1 1 != 11111 111 0 LD4Rregister offset
1 1 11111 000 LD2 (single structure)8-bit, immediate offset
1 1 11111 001 LD4 (single structure)8-bit, immediate offset
1 1 11111 010 x0 LD2 (single structure)16-bit, immediate offset
1 1 11111 011 x0 LD4 (single structure)16-bit, immediate offset
1 1 11111 100 00 LD2 (single structure)32-bit, immediate offset
1 1 11111 100 0 01 LD2 (single structure)64-bit, immediate offset
1 1 11111 101 00 LD4 (single structure)32-bit, immediate offset
1 1 11111 101 0 01 LD4 (single structure)64-bit, immediate offset
1 1 11111 110 0 LD2Rimmediate offset
1 1 11111 111 0 LD4Rimmediate offset

Load/store memory tags

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 1 0 0 1 opc 1 imm9 op2 Rn Rt
Decode fields Instruction Details Architecture Version
opc imm9 op2
00 01 STGpost-index Armv8.5
00 10 STGsigned offset Armv8.5
00 11 STGpre-index Armv8.5
00 000000000 00 STZGM Armv8.5
01 00 LDG Armv8.5
01 01 STZGpost-index Armv8.5
01 10 STZGsigned offset Armv8.5
01 11 STZGpre-index Armv8.5
10 01 ST2Gpost-index Armv8.5
10 10 ST2Gsigned offset Armv8.5
10 11 ST2Gpre-index Armv8.5
10 != 000000000 00 UNALLOCATED -
10 000000000 00 STGM Armv8.5
11 01 STZ2Gpost-index Armv8.5
11 10 STZ2Gsigned offset Armv8.5
11 11 STZ2Gpre-index Armv8.5
11 != 000000000 00 UNALLOCATED -
11 000000000 00 LDGM Armv8.5

Load/store exclusive

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 0 0 1 0 0 0 o2 L o1 Rs o0 Rt2 Rn Rt
Decode fields Instruction Details Architecture Version
size o2 L o1 o0 Rt2
1 1 != 11111 UNALLOCATED -
0x 0 1 != 11111 UNALLOCATED -
00 0 0 0 0 STXRB -
00 0 0 0 1 STLXRB -
00 0 0 1 0 11111 CASP, CASPA, CASPAL, CASPL32-bit CASP Armv8.1
00 0 0 1 1 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPL Armv8.1
00 0 1 0 0 LDXRB -
00 0 1 0 1 LDAXRB -
00 0 1 1 0 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPA Armv8.1
00 0 1 1 1 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPAL Armv8.1
00 1 0 0 0 STLLRB Armv8.1
00 1 0 0 1 STLRB -
00 1 0 1 0 11111 CASB, CASAB, CASALB, CASLBCASB Armv8.1
00 1 0 1 1 11111 CASB, CASAB, CASALB, CASLBCASLB Armv8.1
00 1 1 0 0 LDLARB Armv8.1
00 1 1 0 1 LDARB -
00 1 1 1 0 11111 CASB, CASAB, CASALB, CASLBCASAB Armv8.1
00 1 1 1 1 11111 CASB, CASAB, CASALB, CASLBCASALB Armv8.1
01 0 0 0 0 STXRH -
01 0 0 0 1 STLXRH -
01 0 0 1 0 11111 CASP, CASPA, CASPAL, CASPL64-bit CASP Armv8.1
01 0 0 1 1 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPL Armv8.1
01 0 1 0 0 LDXRH -
01 0 1 0 1 LDAXRH -
01 0 1 1 0 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPA Armv8.1
01 0 1 1 1 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPAL Armv8.1
01 1 0 0 0 STLLRH Armv8.1
01 1 0 0 1 STLRH -
01 1 0 1 0 11111 CASH, CASAH, CASALH, CASLHCASH Armv8.1
01 1 0 1 1 11111 CASH, CASAH, CASALH, CASLHCASLH Armv8.1
01 1 1 0 0 LDLARH Armv8.1
01 1 1 0 1 LDARH -
01 1 1 1 0 11111 CASH, CASAH, CASALH, CASLHCASAH Armv8.1
01 1 1 1 1 11111 CASH, CASAH, CASALH, CASLHCASALH Armv8.1
10 0 0 0 0 STXR32-bit -
10 0 0 0 1 STLXR32-bit -
10 0 0 1 0 STXP32-bit -
10 0 0 1 1 STLXP32-bit -
10 0 1 0 0 LDXR32-bit -
10 0 1 0 1 LDAXR32-bit -
10 0 1 1 0 LDXP32-bit -
10 0 1 1 1 LDAXP32-bit -
10 1 0 0 0 STLLR32-bit Armv8.1
10 1 0 0 1 STLR32-bit -
10 1 0 1 0 11111 CAS, CASA, CASAL, CASL32-bit CAS Armv8.1
10 1 0 1 1 11111 CAS, CASA, CASAL, CASL32-bit CASL Armv8.1
10 1 1 0 0 LDLAR32-bit Armv8.1
10 1 1 0 1 LDAR32-bit -
10 1 1 1 0 11111 CAS, CASA, CASAL, CASL32-bit CASA Armv8.1
10 1 1 1 1 11111 CAS, CASA, CASAL, CASL32-bit CASAL Armv8.1
11 0 0 0 0 STXR64-bit -
11 0 0 0 1 STLXR64-bit -
11 0 0 1 0 STXP64-bit -
11 0 0 1 1 STLXP64-bit -
11 0 1 0 0 LDXR64-bit -
11 0 1 0 1 LDAXR64-bit -
11 0 1 1 0 LDXP64-bit -
11 0 1 1 1 LDAXP64-bit -
11 1 0 0 0 STLLR64-bit Armv8.1
11 1 0 0 1 STLR64-bit -
11 1 0 1 0 11111 CAS, CASA, CASAL, CASL64-bit CAS Armv8.1
11 1 0 1 1 11111 CAS, CASA, CASAL, CASL64-bit CASL Armv8.1
11 1 1 0 0 LDLAR64-bit Armv8.1
11 1 1 0 1 LDAR64-bit -
11 1 1 1 0 11111 CAS, CASA, CASAL, CASL64-bit CASA Armv8.1
11 1 1 1 1 11111 CAS, CASA, CASAL, CASL64-bit CASAL Armv8.1

LDAPR/STLR (unscaled immediate)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 0 1 1 0 0 1 opc 0 imm9 0 0 Rn Rt
Decode fields Instruction Details Architecture Version
size opc
00 00 STLURB Armv8.4
00 01 LDAPURB Armv8.4
00 10 LDAPURSB64-bit Armv8.4
00 11 LDAPURSB32-bit Armv8.4
01 00 STLURH Armv8.4
01 01 LDAPURH Armv8.4
01 10 LDAPURSH64-bit Armv8.4
01 11 LDAPURSH32-bit Armv8.4
10 00 STLUR32-bit Armv8.4
10 01 LDAPUR32-bit Armv8.4
10 10 LDAPURSW Armv8.4
10 11 UNALLOCATED -
11 00 STLUR64-bit Armv8.4
11 01 LDAPUR64-bit Armv8.4
11 10 UNALLOCATED -
11 11 UNALLOCATED -

Load register (literal)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opc 0 1 1 V 0 0 imm19 Rt
Decode fields Instruction Details
opc V
00 0 LDR (literal)32-bit
00 1 LDR (literal, SIMD&FP)32-bit
01 0 LDR (literal)64-bit
01 1 LDR (literal, SIMD&FP)64-bit
10 0 LDRSW (literal)
10 1 LDR (literal, SIMD&FP)128-bit
11 0 PRFM (literal)
11 1 UNALLOCATED

Load/store no-allocate pair (offset)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opc 1 0 1 V 0 0 0 L imm7 Rt2 Rn Rt
Decode fields Instruction Details
opc V L
00 0 0 STNP32-bit
00 0 1 LDNP32-bit
00 1 0 STNP (SIMD&FP)32-bit
00 1 1 LDNP (SIMD&FP)32-bit
01 0 UNALLOCATED
01 1 0 STNP (SIMD&FP)64-bit
01 1 1 LDNP (SIMD&FP)64-bit
10 0 0 STNP64-bit
10 0 1 LDNP64-bit
10 1 0 STNP (SIMD&FP)128-bit
10 1 1 LDNP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register pair (post-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opc 1 0 1 V 0 0 1 L imm7 Rt2 Rn Rt
Decode fields Instruction Details Architecture Version
opc V L
00 0 0 STP32-bit -
00 0 1 LDP32-bit -
00 1 0 STP (SIMD&FP)32-bit -
00 1 1 LDP (SIMD&FP)32-bit -
01 0 0 STGP Armv8.5
01 0 1 LDPSW -
01 1 0 STP (SIMD&FP)64-bit -
01 1 1 LDP (SIMD&FP)64-bit -
10 0 0 STP64-bit -
10 0 1 LDP64-bit -
10 1 0 STP (SIMD&FP)128-bit -
10 1 1 LDP (SIMD&FP)128-bit -
11 UNALLOCATED -

Load/store register pair (offset)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opc 1 0 1 V 0 1 0 L imm7 Rt2 Rn Rt
Decode fields Instruction Details Architecture Version
opc V L
00 0 0 STP32-bit -
00 0 1 LDP32-bit -
00 1 0 STP (SIMD&FP)32-bit -
00 1 1 LDP (SIMD&FP)32-bit -
01 0 0 STGP Armv8.5
01 0 1 LDPSW -
01 1 0 STP (SIMD&FP)64-bit -
01 1 1 LDP (SIMD&FP)64-bit -
10 0 0 STP64-bit -
10 0 1 LDP64-bit -
10 1 0 STP (SIMD&FP)128-bit -
10 1 1 LDP (SIMD&FP)128-bit -
11 UNALLOCATED -

Load/store register pair (pre-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opc 1 0 1 V 0 1 1 L imm7 Rt2 Rn Rt
Decode fields Instruction Details Architecture Version
opc V L
00 0 0 STP32-bit -
00 0 1 LDP32-bit -
00 1 0 STP (SIMD&FP)32-bit -
00 1 1 LDP (SIMD&FP)32-bit -
01 0 0 STGP Armv8.5
01 0 1 LDPSW -
01 1 0 STP (SIMD&FP)64-bit -
01 1 1 LDP (SIMD&FP)64-bit -
10 0 0 STP64-bit -
10 0 1 LDP64-bit -
10 1 0 STP (SIMD&FP)128-bit -
10 1 1 LDP (SIMD&FP)128-bit -
11 UNALLOCATED -

Load/store register (unscaled immediate)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 opc 0 imm9 0 0 Rn Rt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STURB
00 0 01 LDURB
00 0 10 LDURSB64-bit
00 0 11 LDURSB32-bit
00 1 00 STUR (SIMD&FP)8-bit
00 1 01 LDUR (SIMD&FP)8-bit
00 1 10 STUR (SIMD&FP)128-bit
00 1 11 LDUR (SIMD&FP)128-bit
01 0 00 STURH
01 0 01 LDURH
01 0 10 LDURSH64-bit
01 0 11 LDURSH32-bit
01 1 00 STUR (SIMD&FP)16-bit
01 1 01 LDUR (SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STUR32-bit
10 0 01 LDUR32-bit
10 0 10 LDURSW
10 1 00 STUR (SIMD&FP)32-bit
10 1 01 LDUR (SIMD&FP)32-bit
11 0 00 STUR64-bit
11 0 01 LDUR64-bit
11 0 10 PRFUM
11 1 00 STUR (SIMD&FP)64-bit
11 1 01 LDUR (SIMD&FP)64-bit

Load/store register (immediate post-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 opc 0 imm9 0 1 Rn Rt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 UNALLOCATED
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Load/store register (unprivileged)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 opc 0 imm9 1 0 Rn Rt
Decode fields Instruction Details
size V opc
1 UNALLOCATED
00 0 00 STTRB
00 0 01 LDTRB
00 0 10 LDTRSB64-bit
00 0 11 LDTRSB32-bit
01 0 00 STTRH
01 0 01 LDTRH
01 0 10 LDTRSH64-bit
01 0 11 LDTRSH32-bit
1x 0 11 UNALLOCATED
10 0 00 STTR32-bit
10 0 01 LDTR32-bit
10 0 10 LDTRSW
11 0 00 STTR64-bit
11 0 01 LDTR64-bit
11 0 10 UNALLOCATED

Load/store register (immediate pre-indexed)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 opc 0 imm9 1 1 Rn Rt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 UNALLOCATED
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Atomic memory operations

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 A R 1 Rs o3 opc 0 0 Rn Rt
Decode fields Instruction Details Architecture Version
size V A R o3 opc
0 1 001 UNALLOCATED -
0 1 01x UNALLOCATED -
0 1 101 UNALLOCATED -
0 1 11x UNALLOCATED -
0 0 1 100 UNALLOCATED -
0 1 1 1 100 UNALLOCATED -
1 UNALLOCATED -
00 0 0 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDB Armv8.1
00 0 0 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRB Armv8.1
00 0 0 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORB Armv8.1
00 0 0 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETB Armv8.1
00 0 0 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXB Armv8.1
00 0 0 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINB Armv8.1
00 0 0 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXB Armv8.1
00 0 0 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINB Armv8.1
00 0 0 0 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPB Armv8.1
00 0 0 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDLB Armv8.1
00 0 0 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRLB Armv8.1
00 0 0 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORLB Armv8.1
00 0 0 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETLB Armv8.1
00 0 0 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXLB Armv8.1
00 0 0 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINLB Armv8.1
00 0 0 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXLB Armv8.1
00 0 0 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINLB Armv8.1
00 0 0 1 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPLB Armv8.1
00 0 1 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDAB Armv8.1
00 0 1 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRAB Armv8.1
00 0 1 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORAB Armv8.1
00 0 1 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETAB Armv8.1
00 0 1 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXAB Armv8.1
00 0 1 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINAB Armv8.1
00 0 1 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXAB Armv8.1
00 0 1 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINAB Armv8.1
00 0 1 0 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPAB Armv8.1
00 0 1 0 1 100 LDAPRB Armv8.3
00 0 1 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDALB Armv8.1
00 0 1 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRALB Armv8.1
00 0 1 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORALB Armv8.1
00 0 1 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETALB Armv8.1
00 0 1 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXALB Armv8.1
00 0 1 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINALB Armv8.1
00 0 1 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXALB Armv8.1
00 0 1 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINALB Armv8.1
00 0 1 1 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPALB Armv8.1
01 0 0 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDH Armv8.1
01 0 0 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRH Armv8.1
01 0 0 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORH Armv8.1
01 0 0 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETH Armv8.1
01 0 0 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXH Armv8.1
01 0 0 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINH Armv8.1
01 0 0 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXH Armv8.1
01 0 0 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINH Armv8.1
01 0 0 0 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPH Armv8.1
01 0 0 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDLH Armv8.1
01 0 0 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRLH Armv8.1
01 0 0 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORLH Armv8.1
01 0 0 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETLH Armv8.1
01 0 0 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXLH Armv8.1
01 0 0 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINLH Armv8.1
01 0 0 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXLH Armv8.1
01 0 0 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINLH Armv8.1
01 0 0 1 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPLH Armv8.1
01 0 1 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDAH Armv8.1
01 0 1 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRAH Armv8.1
01 0 1 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORAH Armv8.1
01 0 1 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETAH Armv8.1
01 0 1 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXAH Armv8.1
01 0 1 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINAH Armv8.1
01 0 1 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXAH Armv8.1
01 0 1 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINAH Armv8.1
01 0 1 0 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPAH Armv8.1
01 0 1 0 1 100 LDAPRH Armv8.3
01 0 1 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDALH Armv8.1
01 0 1 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRALH Armv8.1
01 0 1 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORALH Armv8.1
01 0 1 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETALH Armv8.1
01 0 1 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXALH Armv8.1
01 0 1 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINALH Armv8.1
01 0 1 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXALH Armv8.1
01 0 1 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINALH Armv8.1
01 0 1 1 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPALH Armv8.1
10 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADD Armv8.1
10 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLR Armv8.1
10 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEOR Armv8.1
10 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSET Armv8.1
10 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAX Armv8.1
10 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMIN Armv8.1
10 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAX Armv8.1
10 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMIN Armv8.1
10 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWP Armv8.1
10 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDL Armv8.1
10 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRL Armv8.1
10 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORL Armv8.1
10 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETL Armv8.1
10 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXL Armv8.1
10 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINL Armv8.1
10 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXL Armv8.1
10 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINL Armv8.1
10 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPL Armv8.1
10 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDA Armv8.1
10 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRA Armv8.1
10 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORA Armv8.1
10 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETA Armv8.1
10 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXA Armv8.1
10 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINA Armv8.1
10 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXA Armv8.1
10 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINA Armv8.1
10 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPA Armv8.1
10 0 1 0 1 100 LDAPR32-bit Armv8.3
10 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDAL Armv8.1
10 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRAL Armv8.1
10 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORAL Armv8.1
10 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETAL Armv8.1
10 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXAL Armv8.1
10 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINAL Armv8.1
10 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXAL Armv8.1
10 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINAL Armv8.1
10 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPAL Armv8.1
11 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADD Armv8.1
11 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLR Armv8.1
11 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEOR Armv8.1
11 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSET Armv8.1
11 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAX Armv8.1
11 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMIN Armv8.1
11 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAX Armv8.1
11 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMIN Armv8.1
11 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWP Armv8.1
11 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDL Armv8.1
11 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRL Armv8.1
11 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORL Armv8.1
11 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETL Armv8.1
11 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXL Armv8.1
11 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINL Armv8.1
11 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXL Armv8.1
11 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINL Armv8.1
11 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPL Armv8.1
11 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDA Armv8.1
11 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRA Armv8.1
11 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORA Armv8.1
11 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETA Armv8.1
11 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXA Armv8.1
11 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINA Armv8.1
11 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXA Armv8.1
11 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINA Armv8.1
11 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPA Armv8.1
11 0 1 0 1 100 LDAPR64-bit Armv8.3
11 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDAL Armv8.1
11 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRAL Armv8.1
11 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORAL Armv8.1
11 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETAL Armv8.1
11 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXAL Armv8.1
11 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINAL Armv8.1
11 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXAL Armv8.1
11 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINAL Armv8.1
11 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPAL Armv8.1

Load/store register (register offset)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 opc 1 Rm option S 1 0 Rn Rt
Decode fields Instruction Details
size V opc option
x0x UNALLOCATED
x1 1 1x UNALLOCATED
00 0 00 != 011 STRB (register)extended register
00 0 00 011 STRB (register)shifted register
00 0 01 != 011 LDRB (register)extended register
00 0 01 011 LDRB (register)shifted register
00 0 10 != 011 LDRSB (register)64-bit with extended register offset
00 0 10 011 LDRSB (register)64-bit with shifted register offset
00 0 11 != 011 LDRSB (register)32-bit with extended register offset
00 0 11 011 LDRSB (register)32-bit with shifted register offset
00 1 00 != 011 STR (register, SIMD&FP)
00 1 00 011 STR (register, SIMD&FP)
00 1 01 != 011 LDR (register, SIMD&FP)
00 1 01 011 LDR (register, SIMD&FP)
00 1 10 STR (register, SIMD&FP)
00 1 11 LDR (register, SIMD&FP)
01 0 00 STRH (register)
01 0 01 LDRH (register)
01 0 10 LDRSH (register)64-bit
01 0 11 LDRSH (register)32-bit
01 1 00 STR (register, SIMD&FP)
01 1 01 LDR (register, SIMD&FP)
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (register)32-bit
10 0 01 LDR (register)32-bit
10 0 10 LDRSW (register)
10 1 00 STR (register, SIMD&FP)
10 1 01 LDR (register, SIMD&FP)
11 0 00 STR (register)64-bit
11 0 01 LDR (register)64-bit
11 0 10 PRFM (register)
11 1 00 STR (register, SIMD&FP)
11 1 01 LDR (register, SIMD&FP)

Load/store register (pac)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 0 M S 1 imm9 W 1 Rn Rt
Decode fields Instruction Details Architecture Version
size V M W
!= 11 UNALLOCATED -
11 0 0 0 LDRAA, LDRABkey A, offset Armv8.3
11 0 0 1 LDRAA, LDRABkey A, pre-indexed Armv8.3
11 0 1 0 LDRAA, LDRABkey B, offset Armv8.3
11 0 1 1 LDRAA, LDRABkey B, pre-indexed Armv8.3
11 1 UNALLOCATED -

Load/store register (unsigned immediate)

These instructions are under Loads and Stores.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
size 1 1 1 V 0 1 opc imm12 Rn Rt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01