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INSR (SIMD&FP scalar)

Insert SIMD&FP scalar register in shifted vector.

Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size110100001110VmZdn

SVE

INSR <Zdn>.<T>, <V><m>

if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer dn = UInt(Zdn);
integer m = UInt(Vm);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D
<m>

Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.

Operation

CheckSVEEnabled();
bits(VL) dest = Z[dn];
bits(esize) src = V[m];
Z[dn] = dest<VL-esize-1:0> : src;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:

  • The MOVPRFX instruction must specify the same destination register as this instruction.
  • The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.
The MOVPRFX instructions that can be used with this instruction are as follows:
  • An unpredicated MOVPRFX instruction.