You copied the Doc URL to your clipboard.

MOV (SIMD&FP scalar, unpredicated)

Move indexed element or SIMD&FP scalar to vector (unpredicated).

Unconditionally broadcast the SIMD&FP scalar into each element of the destination vector. This instruction is unpredicated.

This is an alias of DUP (indexed). This means:

  • The encodings in this description are named to match the encodings of DUP (indexed).
  • The description of DUP (indexed) gives the operational pseudocode for this instruction.

313029282726252423222120191817161514131211109876543210
00000101imm21tsz001000ZnZd

MOV <Zd>.<T>, <V><n>

is equivalent to

DUP <Zd>.<T>, <Zn>.<T>[0]

and is the preferred disassembly when BitCount(imm2:tsz) == 1.

MOV <Zd>.<T>, <Zn>.<T>[<imm>]

is equivalent to

DUP <Zd>.<T>, <Zn>.<T>[<imm>]

and is the preferred disassembly when BitCount(imm2:tsz) > 1.

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in tsz:
tsz <T>
00000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
10000 Q
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm>

Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

<V> Is a width specifier, encoded in tsz:
tsz <V>
00000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
10000 Q
<n>

Is the number [0-31] of the source SIMD&FP register, encoded in the "Zn" field.

Operation

The description of DUP (indexed) gives the operational pseudocode for this instruction.