Signed saturating decrement vector by multiple of 64-bit predicate constraint element count.
Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The results are saturated to the 64-bit signed integer range.
The named predicate constraint limits the number of active elements in a single predicate to:
* A fixed number (VL1 to VL256)
* The largest power of two (POW2)
* The largest multiple of three or four (MUL3 or MUL4)
* All available, implicitly a multiple of two (ALL).
Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
if !HaveSVE() then UNDEFINED; integer esize = 64; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1; boolean unsigned = FALSE;
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.
CheckSVEEnabled(); integer elements = VL DIV esize; integer count = DecodePredCount(pat, esize); bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, e, esize], unsigned); (Elem[result, e, esize], -) = SatQ(element1 - (count * imm), esize, unsigned); Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.
- An unpredicated MOVPRFX instruction.