Load-Acquire Register Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.
For this instruction, if the destination is WZR/ZXR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
bits(64) address; bits(16) data; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); if n == 31 then CheckSPAlignment(); address = SP; else address = X[n]; data = Mem[address, 2, AccType_ORDERED]; X[t] = ZeroExtend(data, 32);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.